BGR soft-start up

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T-14

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Hello, I have adapted 2 soft-start circuit for BGR
and as VDD is rising during 0.1us, it has overshoot(?)
How to solve this problem?
I have searched several papers for start-up, but it seems they don't have this trouble.





 

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Hi @T-14 ,
- What is your VDD voltage? 8V?
- What is your target Vout?
- It seems like your start-up circuit is based on RC constant (time of charging the cap) .Check your start-up currents, at what time it enables the circuit? Is it enabled at all?
- It would be usefull to see how your circuit is loaded too (What is connected to Iref and Vout);
- I don't understand how did you manage to short two nets with different names Vref1 and VOUT. Any mistake here?
 

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Determining the min and max supply risetime is an important pair of "goalposts" and you can spend time badly, trying to get sane response to insane corner conditions.

Very unlikely to get 100ns risetime out of a global power-on as converters all soft-start. Maybe with a hard switch but between source inductance and decoupling still unlikely.

If your problem is an over-the-top response on hard Vdd slew, try a timeout /UVLO that doesn't allow loop amp to start until Vdd is stable and in tolerance.
 
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1) VDD?
VDD = 7V

2) Vout?
I considered its output to 3.3~5V.

3) Start-up current
Current appears from TOP-PMOS-current-sources
which has 100uA~200uA each. same result with & without start-up circuit

My guess : OPAMP drives -> PMOS-Current-Source turns on rapidly

4) Connect
Iref and Vref are connected to another OPAMP Buffer.
as I wished to measure with Oscilloscope.

5) Vref1 - Vout
I intended it, and it works fine after some sort of in-rush current
--- Updated ---

I set VDD's rise time to 0.1us
Because I think I read post on EDAboard -> simulate VDD increasement 1ns, 1us each
Maybe I can start it up slowly - but how much?

I have no idea about UVLO yet,,, it might takes some time to understand it.
are you talking similar like this? adapt to which node?
 
Last edited:

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For this specific purpose, better to stay simple.
What you need, is to hold off enabling until
you have enough headroom for FET stacks to
work, in suppressing spurious dV/dt turnon
the rest of the way up (or even wait until
done, done).

At this kind of supply, a stack of 2 NMOS,
2 PMOS, all diode connected makes a
"good enough" reference for functionality
of shunt switches (like, put one across final
PMOS G-S, "on" by default, "off" when stack
gets "lit up" (exceeds 2VTN+2VTP, plenty
of gate drive, can turn on below desired
LDO output voltage; problem behind that is
error-amp windup, so more shunting there).

If you put a capacitor burden on the bandgap
then on switch-release, soft start is a freebie.
You probably want that filter anyway, with
discharge shunt (so as to release, on cue).
 

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Thank you for your reply.
I have thought for 20 minutes, but it is hard to figure out shut switch concept.
I searched on internet, but there was only rf-related circuits.
 

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1. I am usually using two types of VDD ramps: 1us and 100us, never let me down in real life.
2. I don't really understand your PENB signal. Shouldn't you keep it high (=VDD) for some time until your VDD is settled?
3. Two branches in your Iref section are shorted by name "Vref2" - is that the way it should be?
4. For the debugging purposes, I can recommend disconnecting Soft-Start circuit for now and focus on Start-up circuit operation and the behavior of the PMOS in the output branch (VOUT) (i.e. check Vsg/Vds, Id etc.)
5. Also, what is the purpose of the BJT in the output branch? I cannot see anything like this in the attached schematics.
 

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T-14 said:
Thank you for your reply.
I have thought for 20 minutes, but it is hard to figure out shut switch concept.
I searched on internet, but there was only rf-related circuits.
Click to expand...

I recommend you work from back (output) to front
fixing problems as they appear.

Obviously you need final-FET control. Shunt gate
to source with PMOS under UVLO control. But this
makes the BG error amp "wind up" if it's given power
and signal, potentially "preloaded" to drive VBG
high and hard, so now you get to deal with that.
Like forcing amp inputs to null or jam + input to
Vss and let op amp natral (or burdened) slew be
the "soft" rise master.

The schematics shown, seem prone to mislead.
The lower one disassociates error amp (Va, Vb)
from the bandgap quantities (Vc, Vd) it ought
to be "sniffing". Why? Paper might say.
 

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My 2 cents...

Your problem is that during startup, whether with the startup circuit or without it, that Gate of your PMOS Mirrors gets hard pulled to ground.

This causes a massive amount of inrush current to flow into the Vref1 (Vout) net and the resistor connected there, which is why we see the over shoot.

Possible Solutions
  1. Place a capacitor at the Vref1 net to ground to slow down the charging. You should slow it down enough that by the time the Vref1 net has reached the correct voltage, all the startup related transients have settled.
    1. You will probably need a capacitor anyway to reduce noise and filter out any parasitic coupling.
  2. Do not allow the gate of the PMOS Mirrors to get pulled all the way to ground. You have two NMOS transistors which control the PMOS Mirror Gate voltage.
    1. One is in the Startup Circuit. You can place something (Perhaps a diode or a resistor) in series with that to limit the gate voltage from being pulled down till VSS.
    2. One is in your OPAMP.
      1. You can place a diode at the gate of this NMOS so that it is not turned ON Fully.
      2. Or you can place something in series at its drain (Perhaps a diode or a resistor) in series with that to limit the gate voltage from being pulled down till VSS.
  3. Or you can try both.
P.S. A startup based on VDD ramp speed is not a great idea.
 

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