Hi
BestBench is a VHDL testbench design- and analysis-tool that allows to
design and debug a testbench independently from the circuit design in
an earlier stage of the design process. It is used by VHDL designers to
develop a testbench and to verify their RTL designs faster and easier.
Unlike the manual and tedious testbench design, BestBench automates the
process by creating self-checking, reactive and stand-alone VHDL testbenches.
BestBench provides the VHDL hardware-designer a graphical toolset to
develop and analyze stimuli and expected responses for a given unit
under test (UUT). The result is a self-checking, reactive and stand-alone
VHDL testbench.
1. h**p://www.geocities.com/sandra998dwcb/beast/
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tnx