Best way to constrain a combinatorial feedback path/timing loop?

[rishubnagpal]

Dear all,



I'm attempting to instantiate a Muller C-element based on the work done by [1]. Briefly, this gate only changes its value when both inputs are equal, otherwise it holds its previous value. In the below figure, there is a feedback path from the output O of the LUT to the input I5. Does this path need to be constrained? If so, what would be the best way to do so? The paper gives some timing info for this gate:

" The minimal calculated delay per one single element (including LUT and interconnects) was 491 ps, the maximal value was 713 ps. "

This EE stackexchange answer [2] alludes to a constraint on the feedback path, but there isn't enough detail for me to proceed forward.



Thanks in advance for any insight on this.



[1]: http://dspace5.zcu.cz/bitstream/11025/35432/1/Pfeifer2.pdf

[2]: http://electronics.stackexchange.com/a/222450

Note, this quesiton was crossposted from the xilinx forum here: http://support.xilinx.com/s/questio...-a-combinatorial-feedback-path?language=en_US

 

[kaz1]

I have never heard of it. It seems to be related to asynchronous design which is not recommended in FPGAs. But it could be at research stage. Delay control in FPGAs is notoriously hard to control and varies from build to build. I assume the main concern on feedback path is that you want to save previous output (without any clocking) until inputs are settled. so how much delay would be implementation dependent and then hard to implement.
nevertheless I have implemented small asynchronous feedback based module in FPGA and controlled delay using extra logic for delay. You can also add timing constraints if tool supports that on logic paths.

 

[rishubnagpal]

I have never heard of it. It seems to be related to asynchronous design which is not recommended in FPGAs. But it could be at research stage. Delay control in FPGAs is notoriously hard to control and varies from build to build. I assume the main concern on feedback path is that you want to save previous output (without any clocking) until inputs are settled. so how much delay would be implementation dependent and then hard to implement.
nevertheless I have implemented small asynchronous feedback based module in FPGA and controlled delay using extra logic for delay. You can also add timing constraints if tool supports that on logic paths.

Thanks for you reply. Yes it is for research and am aware of the uncertainty with doing this on FPGAs.

> You can also add timing constraints if tool supports that on logic paths.
Do you have any suggestions for a what sort of constraint to use here?

 

[kaz1]

Thanks for you reply. Yes it is for research and am aware of the uncertainty with doing this on FPGAs.

> You can also add timing constraints if tool supports that on logic paths.
Do you have any suggestions for a what sort of constraint to use here?

The set_max_delay and set_min_delay are first to come to mind. Though they are meant for clocked systems but if you look into details it also applies to cells or ports...etc. Try it. It is likely you will get in a mess of warning due to combinatorial loop. FPGAs are not designed for such async. methodology. The other way is to add delay cells such cascade of inverters but requires preventing optimisation (through keep atribute)