Jester
Full Member level 6
What is the best practice PCB layout wise WRT ground planes under high speed isolators?
We're not supposed to run a high speed line/trace over a split ground plane (EMI wise), however the plane needs to be split for isolation.
Assume the following:
1) 4 layers are available
2) Isolation barrier required between isolated high voltage circuit and low voltage comm circuit that is referenced to earth, say 158mils (4mm)
3) Serial Isolator is https://www.digikey.com/product-detail/en/texas-instruments/ISO7842DW/296-38617-5-ND/5051703 (100Mbps)
I realize mid layers need very little creepage, to satisfy safety/Hi-Pot test, however there would still need to be a gap even on internal layers.
We're not supposed to run a high speed line/trace over a split ground plane (EMI wise), however the plane needs to be split for isolation.
Assume the following:
1) 4 layers are available
2) Isolation barrier required between isolated high voltage circuit and low voltage comm circuit that is referenced to earth, say 158mils (4mm)
3) Serial Isolator is https://www.digikey.com/product-detail/en/texas-instruments/ISO7842DW/296-38617-5-ND/5051703 (100Mbps)
I realize mid layers need very little creepage, to satisfy safety/Hi-Pot test, however there would still need to be a gap even on internal layers.
