Behavioral simulation of gate level - Modelsim

Guys,

In case I use a post APR or post Synthesis netlist in simulation without SDF annotation, I receive timing violations as the timing checks are performed based on default timing in standard cells behavioral model.

I know of a modelsim option called +notimingchecks which is added to vsim arguments to disable timing checks globally. However, my Question is

Does it only disable timing checks and still the outputs are evaluated after the default gate delays ?
Or the gates are treated as RTL where logic have zero delays ?

If they are not treated as zero delay, then how can I instruct Modelsim to assume zero delays and ignore timing specs in std cells behavioral models ?

note : I do not have the RTL for this netlist and I do not need to run timing simulation. It's just included as a submodule in an all-RTL design.

I'm using TSMC 180
Quetsasim 10.3

Only timing checks are disabled using that option in modelsim. The gate delays are considered.

So as you said, only timing checks are disabled means..

The delay calculation is as usual but the timing constraints are not checked .. am i right?

And does the standard cell library have any timing specs and checks?

thanks

S..Ur right
The standard cell library will give us the gate delays, transition times...But no timing checks.

thanks for your answer,

May i know what are these timing checks?

thanks

Setup and hold time checks...