behavioral clock gating & ICG

Hi guys,

I'm using latch based discrete clock gating module. The clock is active high and I sample the enable with an active low latch. So, I'm sure that the latched enable will never toggle @ the clock rising edge

Questions:

1) Do I need to add clock_gating_check in synthesis constraint ?

2) Due to the skew between the clock to AND gated and latch, possible violation could happen. How can I insert ICG instead of discrete clock gating module ?

note : ICG are inserted when the RTL is designed to benefit from automatic clock gating where the enable signal is used as clock enable in the clock process. The situation is not like this. The RTL does not use clock enables. I have to gate the clock using the enable before I feed it to the destination modules.

Well there are many types of clock gating designs defined in the synopsys document. Each design has its own attribute
integrate_clock_gate, pose_latch_control etc....you have to model the "gating element" to the circuit which are trying to use with proper attribute in the .lib. This way the tool will be able to figure out this "element" is being used as a clock gater. For ICG(integrated clock gater: most popular implementation)...there is a particular cell in the library which will be inserted by the tool when you enable clock gating.