princerock
Junior Member level 2
Consider a simple common source with active load circuit as shown below:
Assuming all the transistors work in saturation and assign Vov=Vgs-Vt
The output swing should be: Vdd-Vov1-Vov2
If I want a 2V output swing and Vdd=2.5v, then I can get Vov1+Vov2<0.5v
Then according to other specifications (such as dc gain) I can do raw calculation about the size of M1 and M2 and let them meet the requirement Vov1+Vov2<0.5.
But in simulation, Vds2 is much larger than Vds1 and thus M1 can't work in saturation(Vds1<Vgs1-Vtn). This is because I assume Vds=Vov when I did the calculation but in fact Vds>Vov also makes transistors saturated. Obviously I can see that Vds1+Vds2=Vdd, but how can I calculate Vds1 and Vds2 and make ture Vds>Vov for both transistors?
Assuming all the transistors work in saturation and assign Vov=Vgs-Vt
The output swing should be: Vdd-Vov1-Vov2
If I want a 2V output swing and Vdd=2.5v, then I can get Vov1+Vov2<0.5v
Then according to other specifications (such as dc gain) I can do raw calculation about the size of M1 and M2 and let them meet the requirement Vov1+Vov2<0.5.
But in simulation, Vds2 is much larger than Vds1 and thus M1 can't work in saturation(Vds1<Vgs1-Vtn). This is because I assume Vds=Vov when I did the calculation but in fact Vds>Vov also makes transistors saturated. Obviously I can see that Vds1+Vds2=Vdd, but how can I calculate Vds1 and Vds2 and make ture Vds>Vov for both transistors?