Basys 2 4 digit countern in VHDL

I did my Fisrt FPGA project, that is a free running 4 digit counter, Is working like a charm but I think is to much for to litle.

Is my design ok, ?

Have any way to optimize for less resource.

I'm a newby on FPGA, but a experienced microprocessor programer, I'm afraid to use old stuff that is not the best for Fpga world.

Please coment about this design


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity carlos007 is
Port ( ClckIn : in STD_LOGIC;
ClckOutHigh : out STD_LOGIC; -- clock div 128
ClckOutLow : out STD_LOGIC; -- clock div (128 * 128 )
DispSelect ut STD_LOGIC_VECTOR(3 DOWNTO 0);
DisplaySeg ut STD_LOGIC_VECTOR(6 DOWNTO 0);
DisplayDp : out STD_LOGIC);
function HexTo7Seg (Hexinput : in STD_LOGIC_VECTOR(3 DOWNTO 0)) return STD_LOGIC_VECTOR is
variable tmp : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
CASE Hexinput IS
when "0000" => tmp := "0000001" ; -- 0
when "0001" => tmp := "1001111" ; -- 1
when "0010" => tmp := "0010010" ; -- 2
when "0011" => tmp := "0000110" ; -- 3
when "0100" => tmp := "1001100" ; -- 4
when "0101" => tmp := "0100100" ; -- 5
when "0110" => tmp := "0100000" ; -- 6
when "0111" => tmp := "0001111" ; -- 7
when "1000" => tmp := "0000000" ; -- 8
when "1001" => tmp := "0001100" ; -- 9
when "1010" => tmp := "0001000" ; -- 10 or A
when "1011" => tmp := "1100000" ; -- 11 or B
when "1100" => tmp := "0110001" ; -- 12 or C
when "1101" => tmp := "1000010" ; -- 13 or D
when "1110" => tmp := "0110000" ; -- 14 or E
when others => tmp := "0111000" ; -- 15 or F
end case;
return tmp;
end HexTo7Seg;
function IntToHex (IntInput : in integer range 0 to 15) return STD_LOGIC_VECTOR is
variable tmp : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
CASE IntInput IS
when 0 => tmp := "0000" ; -- 0
when 1 => tmp := "0001" ; -- 1
when 2 => tmp := "0010" ; -- 2
when 3 => tmp := "0011" ; -- 3
when 4 => tmp := "0100" ; -- 4
when 5 => tmp := "0101" ; -- 5
when 6 => tmp := "0110" ; -- 6
when 7 => tmp := "0111" ; -- 7
when 8 => tmp := "1000" ; -- 8
when 9 => tmp := "1001" ; -- 9
when 10 => tmp := "1010" ; -- 10 or A
when 11 => tmp := "1011" ; -- 11 or B
when 12 => tmp := "1100" ; -- 12 or C
when 13 => tmp := "1101" ; -- 13 or D
when 14 => tmp := "1110" ; -- 14 or E
when others => tmp := "1111" ; -- 15 or F
end case;
return tmp;
end IntToHex;
end carlos007;

architecture Behavioral of carlos007 is

signal temporal: STD_LOGIC;
signal temporal2: STD_LOGIC;
signal counter : integer range 0 to 250 := 0;
signal counter2 : integer range 0 to 10000 := 0;
signal dispcounter : integer range 0 to 3 := 0;
signal BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal BCD2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal BCD3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal BCD4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal counterBCD1 : integer range 0 to 15 := 0;
signal counterBCD2 : integer range 0 to 15 := 0;
signal counterBCD3 : integer range 0 to 15 := 0;
signal counterBCD4 : integer range 0 to 15 := 0;
signal counterdivider : integer range 0 to 1024 := 0;

begin
process ( ClckIn) begin
if rising_edge(ClckIn) then
if (counter = 250) then
temporal <= NOT(temporal);
counter <= 0;
if (counter2 = 1000) then
temporal2 <= NOT(temporal2);
counter2 <= 0;
case dispcounter is
when 0 =>
DispSelect <= "0111";
DisplaySeg <= HexTo7Seg(BCD1); -- Number 1
DisplayDp <= '1';
dispcounter <= dispcounter + 1;
when 1 =>
DispSelect <= "1011";
DisplaySeg <= HexTo7Seg(BCD2); -- Number 2
DisplayDp <= '0';
dispcounter <= dispcounter + 1;
when 2 =>
DispSelect <= "1101";
DisplaySeg <= HexTo7Seg(BCD3); -- Number 3
DisplayDp <= '1';
dispcounter <= dispcounter + 1;
when others =>
DispSelect <= "1110";
DisplaySeg <= HexTo7Seg(BCD4); -- Number 4
DisplayDp <= '1';
dispcounter <= 0;
counterdivider <= counterdivider +1;
if counterdivider = 9 then
counterdivider <= 0;
counterBCD1 <= counterBCD1 + 1;
If (counterBCD1 = 9) then
counterBCD1 <= 0;
counterBCD2 <= counterBCD2 + 1;
If (counterBCD2 = 9) then
counterBCD2 <= 0;
counterBCD3 <= counterBCD3 + 1;
If (counterBCD3 = 9) then
counterBCD3 <= 0;
counterBCD4 <= counterBCD4 + 1;
If (counterBCD4 = 9) then
counterBCD4 <= 0;
end if;
end if;
end if;
end if;
BCD1 <= IntToHex(counterBCD1);
BCD2 <= IntToHex(counterBCD2);
BCD3 <= IntToHex(counterBCD3);
BCD4 <= IntToHex(counterBCD4);
end if;
end case;
else
counter2 <= counter2 + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
ClckOutHigh <= temporal; -- Shows clock high on JD1 to verify with a scope = 50Mhz / 128
ClckOutLow <= temporal2;-- Shows clock low on JD2 to verify with a scope = 50Mhz / ( 128 * 128 )

end Behavioral;