Basics for BPSK modulation in verilog

I want to implement BPSK modulator and demodulator in verilog on spartan 3 kit.
If anyone has done that on any fpga, i request your guidance...

I know the concept that for transmitting '0', we send the sinusoid as it is and for '1' we add 180 phase shift to the sinusoid.

I request guidance on following points
- BPSK modulator, demodulator blocks those can be coded in verilog and ported to an FPGA.
- How do we generate I and Q sinudoid in fpga?
- Can we use only one one sine wave and its inverted version and give it to a 2:1 mux inputs with select line supplied by input data to be modulated. here for '0' information bit we can pass sine wave and for '1' we can send the inverted version.
- Can we use the DCM(Digital Clock Manager) of the FPGA for BPSK modulation?

Thanx in advance.

hello
Please help me if you solved your problem because i am facing it now
thank you

- - - Updated - - -

hello
Please help me if you solved your problem because i am facing it now
thank you

If you are implementing it in FPGA then first run your module in MATLAB.

See the output of osk modulator for m ary number = 2.
You will get a complex number.

I gave fixed binary number for real and complex values of '1' bit and '0' bit.

Tell me if you need more clarification. I suggest to read theory for psk modulation because after then FPGA implementation becomes quite easy.

What help do you need??

I am havein I , Q each 7 bits
I use cordic to get the phase

here you are

// 7 bit input for x, y
// 8 bit input for phase, including highest order bit (pi)
// reference:
// **broken link removed**

`timescale 1ns / 1ns

module addsub(a,b,sum,control);
parameter size=7;
input [size-1:0] a, b;
input control;
output [size-1:0] sum;
assign sum = control ? (a + b) : (a - b);
endmodule

module cstage(xin, yin, zin, ain, xout, yout, zout);
parameter shift=0;
parameter zwidth=7;
parameter width=7;
input [width-1:0] xin, yin;
input [zwidth-1:0] zin, ain;
output [width-1:0] xout, yout;
output [zwidth-1:0] zout;

wire control=zin[zwidth-1];
addsub #( width) ax(xin, {{(shift){yin[width-1]}},yin[width-1:shift]}, xout, control);
addsub #( width) ay(yin, {{(shift){xin[width-1]}},xin[width-1:shift]}, yout, ~control);
addsub #(zwidth) az(zin, ain , zout, control);
endmodule

module cordic(clk, xin, yin, phasein, xout, yout, phaseout);

input clk;
input [6:0] xin, yin;
input [7:0] phasein;
output[6:0] xout, yout;
output[7:0] phaseout;

wire [6:0] xw0, xw1, xw2, xw3, xw4, xw5, xw6, xw7;
wire [6:0] yw0, yw1, yw2, yw3, yw4, yw5, yw6, yw7;

reg [6:0] x0, x1, x2, x3, x4, x5, x6, x7;
reg [6:0] y0, y1, y2, y3, y4, y5, y6, y7;

reg [6:0] z0; wire [6:0] zw0;
reg [6:0] z1; wire [6:0] zw1;
reg [5:0] z2; wire [6:0] zw2;
reg [4:0] z3; wire [5:0] zw3;
reg [3:0] z4; wire [4:0] zw4;
reg [2:0] z5; wire [3:0] zw5;
reg [1:0] z6; wire [2:0] zw6;

// signed 16-bit input angle [-64 , 63] represents the range [ -pi/2 , pi/2 )
// atan((0.5).^[0:12]')/(2*pi)*16*4
// floor(atan((0.5).^[0:14]')/(2*pi)*2**(8)+.5)
// keep one high order 0 bit so these are valid signed numbers

wire [6:0] a0 = 32; // pi/4
wire [6:0] a1 = ;16
wire [5:0] a2 = ;8
wire [4:0] a3 = ;4
wire [3:0] a4 = ;2
wire [2:0] a5 = ;1


assign xout = x6;
assign yout = y6;
assign phaseout = z6;

// zero stage: doesn't quite fit the pattern
addsub #(7) ax0 (7'd0, xin, xw0, ~phasein[7]^phasein[6]);
addsub #(7) ay0 (7'd0, yin, yw0, ~phasein[7]^phasein[6]);
assign zw0 = phasein[6:0];

// first stage: can't use cstage because repeat operator of zero is illegal
addsub #(7) ax1 (x0, y0, xw1, z0[6]);
addsub #(7) ay1 (y0, x0, yw1, ~z0[6]);
addsub #(7) az1 (z0, a0, zw1, z0[6]);

cstage #( 1, 7, 7) cs1 (x1, y1, z1, a1, xw2, yw2, zw2);
cstage #( 2, 6, 7) cs2 (x2, y2, z2, a2, xw3, yw3, zw3);
cstage #( 3, 5, 7) cs3 (x3, y3, z3, a3, xw4, yw4, zw4);
cstage #( 4, 4, 7) cs4 (x4, y4, z4, a4, xw5, yw5, zw5);
cstage #( 5, 3, 7) cs5 (x5, y5, z5, a5, xw6, yw6, zw6);

always @ (posedge clk) begin
x0 <= xw0; y0 <= yw0; z0 <= zw0;
x1 <= xw1; y1 <= yw1; z1 <= zw1;
x2 <= xw2; y2 <= yw2; z2 <= zw2;
x3 <= xw3; y3 <= yw3; z3 <= zw3;
x4 <= xw4; y4 <= yw4; z4 <= zw4;
x5 <= xw5; y5 <= yw5; z5 <= zw5;
x6 <= xw6; y6 <= yw6; z6 <= zw6;
end

endmodule

am i right ??

Sorry.........

don't have any idea of CORDIC implementation.

I suggest if you want to verify your code then do co simulation in MATLAB.
I hope you will find your way out.