Basic Verilog syntax: Zero on left in square-bracket-pair

3pitom3 · Jun 5, 2014

I have a basic Verilog-syntax question, but had trouble finding info on the web, hard to figure out the right keyterms to search...

I wonder what this does:

wire [3:0] foo;
assign foo = bar[0:3];

Why invert the 0 and 3?

I saw this in here:
**broken link removed**
On this line:
reg [p1width - 1 : 0] arr[0: ((p2depth >= 2) ? (p2depth-2) : 0)];

Quartus compiles this, but Odin doesn't like it.

Thanks!

rberek · Jun 5, 2014

Hi

As an example, the PowerPC processor data bus is numbered such that the MSB is 0 and the LSB is 31 (data[0:31]). In the project I worked on, the processor interface RTL code used increasing part-selects (e.g. bar[0:31] ) for data buses connecting to the PowerPC to avoid confusion when discussing these interfaces. But, it added confusion to the rest of the design as the increasing part-selects had to eventually connect to the more standard standard signals (e.g. foo[31:0]).

This was a big PITA, believe me! Avoid it as much as possible.

r.b.

Basic Verilog syntax: Zero on left in square-bracket-pair

3pitom3

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rberek

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Basic Verilog syntax: Zero on left in square-bracket-pair

3pitom3

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rberek

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