basic question reagrding LDO design

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amarendrap14

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ldo basics

i wanted to know what is the correlation between output impedence and LDO transient load performance . actually i am seening a peak of 20db impedence at around UGB of LDO (dc is only around 0 db). however when we apply transient LOAD the measured dip in LDO output is quit less than by simple impedence calculation.
any explanation??


also is there any better way to measure stability of LDO apart from PM and GM.
 

ldo current difference switch

What is your load?., The numbers you quote for output impedance are simulated in no load or with the load that you do the transient sim?
 
ldo & ripple

my load current varies from 50uA to 20mA
the transient load applied is 50uA to 10mA in 50 ns.
the 20 db number is for 20mA , for 50uA (minimum load) the output impedence peaks to 30dB ..
 

ldo design and calculation

Your impedence which you measure is only at one frequency and the transient is effective response for a step input (which has all the frequencies).

If you give a sin wave load of frequency equal to your UGB you will see the drop corresponding to the resistive impedence.
 
ldo basic


how much your output impendance of your circuit will determine how much your LDO output's ripple.


for example your output impedance is 1 ohm at 1 Mhz.

and your output current is vary from 2-4 mA

then your LDO's output ripple is 1 ohm x 2 mA at 1 MHZ.
 
ldo design




but why i am not getting the value corresponding to the output impedence value.
say i apply step of 1mA at the LDO output then i should get 100*1mA = 100mV change in output . i am seeing only 10mV change . i think the step signal does have all frequency component , so frequency component corresponding to ugb will give 100mV voltage component . or there is anything wrong in my frequency- time understanding.
 

ldo basic

I suspect the way in which you are testing your LDO. Do you have a dc current source at the output and switch it's current? This way the drop at the output will correspond to the dc load regulation value.
Have a sine current source, run it at the UGB frequency at the rated current and see the drop at the LDO. This should match with the ac results.
 
gm ldo


thanks saro,
i am seeing the same volatge change in output as claculated from output impedence .(ie 100mV for 1mA @ ugb (50MHz) if output impedence is 100 (40dB)).
actually i was taking only single step earlier . if we take periodic load then the dip will becomes same as what perdicted by output impedence.


is anything i can do to improve output impedence @ ugb . my LDO uses 500pf internal decap and no external cap . drop of 150mV . 1.05 output volatge in 45 nm. max load current of 20mA. Iqq=100uA
 

ldo design step

It is hard to suggest anything without looking at the circuit and it's other specifications. There are various compromises involved. There is no general rule that would enhance every specification.
 

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