Re: basic question on pll
1. Reference spurs are the spectral peaks that one gets to see in the output frequency spectrum of a PLL spaced at integer multiples of the reference frequency from the carrier frequency. Phase noise is due to the inherent noise present in any component in addition to supply/substrate induced noise, reference spurs, noise from reference, etc. In general anything that affects the zero crossing of the output clock is termed as phase noise. But the term phase noise is loosely used to mean the noise arising out of the devices.
Reference spurs increase phase noise. A pss+pnoise simulation for the closed loop PLL would show the complete spectrum that contains reference spurs in addition to phase noise from other sources, but that would be costly in terms of simulation run time and resources.
2. Fractional spurs are common in Fractional-N pll. The integer divider is made to divide by a fractional number by alternating the division ratio over a few cycles. This generates instantaneous phase error at the input which manifests as fractional reference spur. Sigma delta modulation can be used to push this phase error to higher frequencies to take advantage of the loop-filter.
3. If the fractional spur increases, the causes could be
i. PFD-CP becomes non-linear
ii. The division ratio N reduces
iii. BW increases
iv. SD is fed with a constant input without dither
Increasing the CP current increases the BW of the loop if everything else is to remain the same. This would reduce the phase noise from the VCO but would reduce the attenuation for the fractional spurs.