basic question about gain calculation

[princerock]

Hi,

I'm a beginner to Analog IC Design. And I got lost when I took some hand on calculations about the circuit. For example, to calculate a single CS stage with current source load. I know that the gain equals to -gm(ro1||ro2), and that gm equals to (k'(W/L)Id)½ and ro equals to (1/λId). However, how can I decide the Id if I want to calculate the gain of this circuit before doing simulation? Shoud I just assign a arbitrary value to Id (100uA, for example)? How about λ? I am now using tsmc25 technolog and find λ is not a memeber in the tech file (maybe this is because λ is inverse proportion to L?)

 

[sunking]

yes, λ will vary with the L.
And you get the the crude value for hand calculation.
For the opa design with some process, you can refer to the book
cmos analog circuit desing
allen
Chap 5 and 6

 

[muoinhohn]

k', W, L, V_t are the parameters of MOSFET. So they are dependent on the particular MOSFET. They are given by productors.
In the saturation mode, you can canculate the Id = 1/2 k' (W/L) (V_GS -V_t)².

 

[suria3]

Hi,

In the opamp design, first u assume the amount of current to flow at the tail, let say about 100uA. Then to find out the value of λ, take a single PMOS or NMOS. You fix the gate voltage and u sweep the VDS (Drain voltage). Later you plot the curve IDS Vs VDS. So, you can measure the value of ro (output impedance) from the slope. Then convert to λ = 1/ID*ro. Then in order to calculate the transconductance gm value, u can find the value unCox from the simulation list from the particular transistor or from the design manual. Hope this helps you.

Regards,
Suria3

 

[princerock]

Thank you for all of the above

To suria3: I tried your method. But what kind of test circuit should I have? If it is CS with resistor load, the ro is infulenced by the value of the load. Or should it be CS with current source load?

My transistor is not short channel (L=1.5µm). So I guess the λ should be a small number, right?

Added after 4 minutes:

by the way, should I add a dc value to the signal (a vsin in cadence) when I carry on the simulation? Now I set the ac amp of the vsin to 1. It is said that in this way I can get the gain directly from the plot.

 

[suria3]

Hi Princerock,

When you measure the ro of the NMOS, the drain of the NMOS you give dc value (sweep) without any load (RL) connected to the drain. This is only to find the effect of ro or λ of the NMOS. Then when it comes for the gain calculation for a simple CS amplifier, the gain is gmRL, where teh effect of ro is ignored as ro||RL, and is effect the RL as the load. You can use as simple CS stage to test out this effect.

As we know that, L ≈ 1/λ, since your L size is big, the effect of λ could be lesser. That's why in the differential amplifier design, normally we see set the value of L to be 2 or 3 x than effective length of the tail transistor to minimize the effect of λ as the total gain of the diffamp is controlled by the switching current at the tail.

Well, to find out the gain of your CS amplifier, u give the dc voltage and AC=1 at the gate of NMOS or PMOS with load RL connected at the drain. Then you plot the Vout/Vin and scale it in logaritmic. I'm sure you will see the gain of your circuit in db.

Hereby i'm attaching 2 papers which will help you on the simulation.

Regards,
Suria3