In an single nwell process, am I correct in assuming that all nmos devices have to have their body connected to vss (even if their source is not)? The bias current mirror device is currently in between vss and the common source of my input stage, so Vb != Vs. Is it better to make this p-type and connect the current mirror to vdd?
If what I understood is correct, then you are biasing your stage with an NMOS current mirror. In this case, the MOS mirror operates with Vb = Vs = Vss. The biased NMOS pair however would have a higher Vth due to body effect ( which is usually not a big problem ).
Of course you can use PMOS pairs instead. this will have the advantage of a lower Vth ( and hence a higher common-mode input range ). However, this comes at the cost of lower gm of PMOS devices ( for same area as NMOS ). To get same gm from PMOS, you would need roughly 3 times the area of the NMOS pair.