Caspar
Newbie level 2
Hi,
In an single nwell process, am I correct in assuming that all nmos devices have to have their body connected to vss (even if their source is not)? The bias current mirror device is currently in between vss and the common source of my input stage, so Vb != Vs. Is it better to make this p-type and connect the current mirror to vdd?
Thanks for your consideration,
Caspar
In an single nwell process, am I correct in assuming that all nmos devices have to have their body connected to vss (even if their source is not)? The bias current mirror device is currently in between vss and the common source of my input stage, so Vb != Vs. Is it better to make this p-type and connect the current mirror to vdd?
Thanks for your consideration,
Caspar