Basic doubt about signals in VHDL

Hey

I start learning VHDL with a Xilinx Spartan 3E SK and bassically my question is that if I assign a '0' to a std_logic signal it will be connected to ground? If not, how can I connect a signal to ground or simulate a virtual ground?

Thanks everybody, and sorry for my poor english... I understand but not know how to speak/write english very well

If this signal drives logic - then the pin of that logic will be connected to ground.

to simulate:
x <= '0' ;

InfiniteLoop said:

Hey

I start learning VHDL with a Xilinx Spartan 3E SK and bassically my question is that if I assign a '0' to a std_logic signal it will be connected to ground? If not, how can I connect a signal to ground or simulate a virtual ground?

Thanks everybody, and sorry for my poor english... I understand but not know how to speak/write english very well

Click to expand...

1/ it won't be connected to ground.
2/ virtuall ground mabee but only ... a/ if you connect it to output pin and drive it to '0'
or
b/ put the output it to 3-state , and use internal pull-down - but this will only work for small currents, and can gepeordise your fpga.
3/ why do you want to ground a signal or use it as ground ?
4/ only thing that comming to my mind is that you want to activate some external device that need a GND connection , like a horn, or electric lock.
in this case you will need to connect your output pin to a relay device, that will be connected to GND.

aruipksni,

A signal that's '0' is essentially connected to ground (switched to ground by the logic device's transistors)...

Not '0' is logic '0', not ground. So, for example, it would not be recommended to connect the ground pin of a chip to an FPGA pin held at '0', as the level may not match the level of ground on the ground plane on a board.

InfiniteLoop said:

Hey

I start learning VHDL with a Xilinx Spartan 3E SK and bassically my question is that if I assign a '0' to a std_logic signal it will be connected to ground? If not, how can I connect a signal to ground or simulate a virtual ground?

Click to expand...

If you're just trying to simulate, then yes the statement "a <= '0';" will simulate exactly the same as if 'a' was connected to ground.

If you're talking about synthesizing a design that you will download to a device then there is nothing that will connect a signal to ground. Instead what happens is that the logic that gets implemented will be optomized. A simple example:

d <= c or b or a;
a <= '0';

What gets synthesized then will be

d <= c or b;

There will be no signal 'a' implemented because the effects of 'a' have been incorporated into the logic of any signal that 'a' affected.

Kevin Jennings