Basic digita ASIC flow

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nathan11

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Hi all, I am a master's student, and new to this field

I wrote some basic verilog RTL code and test bench. I synthesize the code (except testbench) using Synopsys design analyzer. Now I want to verify the synthesized code by simulation. this case I am using ModelSim simulator. I am not sure which file (gate level netlist) I need to get it from Design Analyzer to ModelSim.

thanks in advance
 

You must use verilog output format and load synthesized code in verilog (verilog netlist) in modelsim or over simulator. Also you can use VHDL netlist.
 

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    nathan11

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once you read your design in to the design analyzer and after it is compiled, u can use write_verilog command available for generating the gate level netlist for your top level design or any of sub-blocks of the top level design.
 

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    nathan11

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Thanks guys for your reply
do you know the file extension of the output netlist ( I am bit confused ) original RTL code and the verilog code after compilation

thanks again
 

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