library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DAC_8811_top is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DAC_MOSI : out STD_LOGIC;
data_complete : out STD_LOGIC; -- reports to Demodulation block upon sending complete data (added later by varun)
start_data : in STD_LOGIC; -- receives command from Demodulation block to send data.(added later by varun)
DAC_SCK : out STD_LOGIC;
DAC_CS : out STD_LOGIC;
DEMOD_CLK : in STD_LOGIC; --- clock for demodulator data(added by varun LAter) (1320 demod clok period)
TX_DATA : out signed (16 downto 0)); -- data for demodulator block (added later by varun)
end DAC_8811_top;
architecture Behavioral of DAC_8811_top is
signal rdy,daccs,dacsck,dacmosi : std_logic;
signal dacdata : unsigned(15 downto 0);
signal pattern : unsigned(15 downto 0);
type memory_type is array (0 to 24) of integer range 0 to 65535; -- dac8811 will receive only 24 points but for demodulator 25 points will be available
signal sine : memory_type :=( 32767,40609,47995,54496,59735,63406,65296,63406,59735,54496,47995,40609,32767,24924,17538,11037,5798,2129,238,2129,5798,11037,17538,24924,32767);
-- signal clk_div : std_logic := '0'; -- later added by varun
type state_type is (send,stop); -- later added by varun
signal state : state_type := send; -- later added by varun
component DAC_SPI
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DAC_DATA : in unsigned(15 downto 0);
DAC_MOSI : out STD_LOGIC;
DAC_SCK : out STD_LOGIC;
DAC_CS : out STD_LOGIC;
RDY : out STD_LOGIC);
end component;
begin
U1_1 : DAC_SPI Port map ( CLK => CLK, RST => RST, DAC_MOSI => dacmosi, DAC_SCK => dacsck, DAC_CS => daccs, RDY => RDY, DAC_DATA => dacdata);
process(RST,CLK,daccs,dacsck,dacmosi)
variable temp : integer;
variable i : integer range 0 to 24 := 0;
begin
if (RST='1') then
DAC_MOSI <= '0';
DAC_SCK <= '0';
DAC_CS <= '1';
elsif falling_edge(CLK) then
if (rdy = '1') then -- Check if first 32 bits is sent and proceed to the next
pattern <= to_unsigned(sine(i), 16); -- 16 bit value to change your output analog value, set your corresponding 16 bits digital value here.
i := i + 1;
if(i = 24) then
i := 0;
end if;
dacdata(15 downto 0) <= pattern;
end if;
end if;
DAC_CS <= daccs;
DAC_SCK <= dacsck;
DAC_MOSI <= dacmosi;
end process;
process (CLK,DEMOD_CLK,start_data)
variable k : integer range 0 to 25 := 0;
begin
if rising_edge(DEMOD_CLK) then
if(start_data ='1')then
case state is
when send =>
data_complete <= '0';
TX_DATA <= to_signed(sine(k),17);
k := k+1;
if (k = 25)then
state <= stop;
else
state <= send;
end if;
when stop =>
k := 0;
TX_DATA <= (others => '0');
data_complete <= '1';
state <= send;
end case;
end if;
end if;
end process;
end Behavioral;