Bandgap startup circuit simulation and question

[Warlike]

start up circuit

I designed Bandgap voltage reference and startup circuit for it. I have read topics about BGVR and startup. I verify startup this way: make Vdd constant value (or use vpwl source and ramp on Vdd), set initial conditions for nodes and make transient simulation.

Vref reaches desired value over time 1-2 us with start up circuit and over time 200-300 ms without it.

I have some questions.
1) Are this way of verify startup right?
2) What's mean steady state of BGVR? (i mean zero state). Does it mean that BGVR will not start never or it's mean that BGVR will start over very long time (~hundred ms)?

 

[ytliang]

startup circuit

1. I think it is right, but you have to make sure your initial conditions are reasonable.

2. In the zero state, bandgap reference output would be very low. It will be stuck there forever and never start.

 

[leehying]

bandgap startup circuit

Hi,
Beside ramp VCC. If your BGR got a Enable controlling signal, step it when VCC is OK.
Best regards.
ELE

 

[winsonpku]

startup circuits

1.what is your initial seting for your circuit or why you do that?
Becuase you have an inable pin?
2. The mean state is a stable state and in this state the VBGR will not start ever without start-up circuit.

I designed Bandgap voltage reference and startup circuit for it. I have read topics about BGVR and startup. I verify startup this way: make Vdd constant value (or use vpwl source and ramp on Vdd), set initial conditions for nodes and make transient simulation.

Vref reaches desired value over time 1-2 us with start up circuit and over time 200-300 ms without it.

I have some questions.
1) Are this way of verify startup right?
2) What's mean steady state of BGVR? (i mean zero state). Does it mean that BGVR will not start never or it's mean that BGVR will start over very long time (~hundred ms)?

 

[absjoshi]

bandgap startup

The bandgap circuit has two stable operating points. One is at zero current and the second one is at the designed current in the loop. In order to prevent the circuit to get locked in the zero current state, the start up circuits are used. But in reality there is parasitic capacitance associated with every node. hence these caps are sufficient to bring the circuit out of the zero current state...however this may take unpredictable amount of time....hence to avoid such unpredictability, a startup circuit is used which for sure prevents circuit to get locked in the zero current state.
But it is very unlikely that bandgap will not reach to its steady state value at all without a start up circuit.

 

[saro_k_82]

bandgap circuit

The bandgap circuit has two stable operating points. One is at zero current and the second one is at the designed current in the loop. In order to prevent the circuit to get locked in the zero current state, the start up circuits are used. But in reality there is parasitic capacitance associated with every node. hence these caps are sufficient to bring the circuit out of the zero current state...

Can you explain how the parasitic caps help you get your circuit out of the zero state?
IMO larger parasitic caps., the probability of your circuit coming to active state decreases...

But it is very unlikely that bandgap will not reach to its steady state value at all without a start up circuit.

It is rather easy for a BGR to get locked in zero state without a startup ckt. I have experienced 10% failure in my chips that had the startup failure because of a resistor being open in the startup circuit (which eventually shut the start-up block)

 

[bharatsmile2007]

start-up circuit

hi

can any one pls explain how BGR attains zero current state?

Thanks

 

[saro_k_82]

startup circuit bandgap

hi

can any one pls explain how BGR attains zero current state?

Thanks

When there is zero current through the bjts, the voltage input to the opamp will also be at zero. There will not be any considerable difference between the two opamp input voltages which are at zero. So the error amp will not see any problem and it will not correct for it.., and it will try to suppress any disturbance that causes to bring it out of the zero current state. So the BGR can forever be in the zero-state if it is not forced out of it by a start-up.
Hope this helps...

 

[bharatsmile2007]

start up circuits

Thank you saro_k_82....

 

[bharatsmile2007]

startup bandgap

hi all,

would you pls clarify me on startup circuit simulation in BGR..

do i need to connect any load(load current specified for the bandgap),while transient simulation for the startup circuit?

Thanks

 

[saro_k_82]

start up circuit

I don't think you are loading the bandgap core., you must have buffered it. In any case startup should be independent of the load.

 

[bharatsmile2007]

bandgap start up

hi war like

what is the VDD ramp you used for the simulation ?


I designed Bandgap voltage reference and startup circuit for it. I have read topics about BGVR and startup. I verify startup this way: make Vdd constant value (or use vpwl source and ramp on Vdd), set initial conditions for nodes and make transient simulation.

Vref reaches desired value over time 1-2 us with start up circuit and over time 200-300 ms without it.

I have some questions.
1) Are this way of verify startup right?
2) What's mean steady state of BGVR? (i mean zero state). Does it mean that BGVR will not start never or it's mean that BGVR will start over very long time (~hundred ms)?