Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

bandgap reference - need suggestions on the topology

Status
Not open for further replies.

crazyfox

Junior Member level 2
Junior Member level 2
Joined
May 12, 2007
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,452
bandgap reference

HI :

I am trying to design a bandgap , and the topology is like below ,

The supply voltage is between 2.4 to 5.8 (v) , and i use .6um process

The temperature is vary from -40 to 130 degree

The opamp that i used has 75 (dB) gain and 60 phase margin

My question is that, when the supply voltage is larger the curve like below

seems not correct, but i have sure that the output stage has enough drive

current, and opamp gain and phase margin is enough .

Can anyone give me some suggestion that any thing i didn't concern?

Thx!


 

Re: bandgap reference

You should simulate your ckt in different corners, rather than in different supply voltage alone.
 

Re: bandgap reference

please make sure your opamp work in the correct state
 

Re: bandgap reference

Dear crazyfox,

Your circuit seems working, and it's natural that BGR behavior varies with VDD from 2.8V to 5.5V. You can check if DC operating points all shift.
One common solution to this problem is to add LDO on top of BGR unless you would like to try very high PSRR opamp (some literatures can also br found for these school of circuits).

Have fun,
 

Re: bandgap reference

As some one also said, the band gap reference only works if we have an IDEAL op map during the whole range. I think your op amp stops working after a certain point.

Take care
 

bandgap reference

Hi,

It doesn't seem too bad, but I agree that it could be improved. 75 dB should be enough gain to keep this profile correct from 2v-6v.

Maybe you get an offset current you weren't expecting.

I'd have to see your op amp to be sure, but I am guessing that somewhere (in a cascode, or just a source follower) you use an NMOS whose body is tied to source, and whose source is not ground.

Therefore, any impact ionization from the increased input voltage will cause your drain current to increase and it will affect the operating point of your amp.

Try looking for the body current in simulation, or just tie all the bodies to ground and see if your bg profile is fixed.
 

Re: bandgap reference

Hi,

To be sure that the AOP is the affected Bloc, you can simulate with an ideal AOP.
 

Re: bandgap reference

What's youy Opamp's GBW? How to derive it from?


crazyfox said:
HI :

I am trying to design a bandgap , and the topology is like below ,

The supply voltage is between 2.4 to 5.8 (v) , and i use .6um process

The temperature is vary from -40 to 130 degree

The opamp that i used has 75 (dB) gain and 60 phase margin

My question is that, when the supply voltage is larger the curve like below

seems not correct, but i have sure that the output stage has enough drive

current, and opamp gain and phase margin is enough .

Can anyone give me some suggestion that any thing i didn't concern?

Thx!


 

Re: bandgap reference

Do you have a start-up circuit?
 

Re: bandgap reference

you'd better check the dc point of the apamp making sure the correct function of locking the input voltage the same.
according to the curves, the temperature at Tc=0 changed because of the current flowing through the transistors. This is just my guess.
Would you like to show the schematic of opamp? I am curious about the buffer stage. Thank you
 

Re: bandgap reference

crazyfox said:
HI :

I am trying to design a bandgap , and the topology is like below ,

The supply voltage is between 2.4 to 5.8 (v) , and i use .6um process

The temperature is vary from -40 to 130 degree

The opamp that i used has 75 (dB) gain and 60 phase margin

My question is that, when the supply voltage is larger the curve like below

seems not correct, but i have sure that the output stage has enough drive

current, and opamp gain and phase margin is enough .

Can anyone give me some suggestion that any thing i didn't concern?

Thx!



Please post your OPAMP circuit.

What is the current for each branch across the temp range at different VDD?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top