Bandgap in SOI
I've designed and tested parts up to 300C, and still had tolerable
functionality. 8-bit ADC, 40V op amps, etc. all work fine as long
as you have the big lightly-doped junctions under control.
SOI does that.
I never looked at a bandgap though. I would rather do a zener
reference if I had the headroom, a lot simpler to make temp-
stable / linear.
If you fit the models past where you will operate, you can
design. It's extrapolating from (say) a 125C data point by
another 150 degrees, that's liable to give you a hoax.
The most annoying things I see on SOI bandgaps, which I have
done (but not taken to high temp) are RTN and kink effects. The
former can result in a bimodal output voltage, which can't be
modeled, is very random (duh) and can bother testing in
production (especially if drift is spec'd, not just a fat window).
The latter I have been modeling behaviorally as an overlay
excess drain conductance.
You will likely find that similar stuff is needed for temperature,
older models (do not know about BSIMSOI et al) did not model,
but neglected generation /recombination currents which are
the big deal at high temp.