Bandgap circuit and simulation.

[Question]

It is a bandgap design, the picture below is the schematic. Bandgap output voltage is 1.22V, and I need 2.1V output voltage. The M1 and M2 are diode-connected as resistors.

It very hard to design w/L of M1&M2. The simulation result is very strange. I think the resistance of M1(or M2) equal to 1/gm. So I should make gm1/gm2=4/3, i.e. W1/W2=16/9. But in fact, I must make W1/W2 more than 10 times, then I can get 2.1V output. I am afraid that the ratio of M1 and M2 is too big will introduce mismatch problem in my layout design. If I take large L (more than 3u, I use TSMC 0.18u process), the performance of temperature-independent will come worse.

In my simulation in ideal conditon, I use a small capacitor as load of output. Then in whole system simulation the load of output is a DAC circuit. I think the output voltage will reduce, when I change the load from a small cap to a DAC. But the result is it increase. I can not understand why the output increase.

Who can give me some advice of the design of M1&M2, and why the voltage increase.

Thanks a lot!!

 

[eda4you]

Maybe its better to use a sc capacitor amplifierer (v bandgap = input) since the accuracy only depends on capacitor mismatch (almost).
A drawback will be a larger amount of area!

 

[Hughes]

Where are the substrate terminals M1 and M2 connected? In the figure, they are connected to "D" terminal. A mistake in this figure?

 

[Question]

Where are the substrate terminals M1 and M2 connected? In the figure, they are connected to "D" terminal. A mistake in this figure?

It connect to AVDD, 3.3V voltage.

 

[Fom]

They should be connected to D terminals, as Hudges wrote. Otherwise output voltage will be changed with AVDD change. Also it can be changed for different corners.

 

[v_naren]

correct me if I am wrong pple!!!!

but I think that the gate is tied to the source!!!!


the gate needs to be tied to the drain.

 

[jordan76]

M1 and M2 are both PMOS whose substrate should be connected to their source respectively to eliminate body effect.

Please correct me if I am wrong.

regards,
jordan76

 

[v_naren]

I only say that the gate should be tied to the drain is it not?

I am not talking abt substrate at all...u can tie sub to source to eliminate body effect

 

[Fom]

Sorry! It should be connected to Source of course. But usually instead of PMOS is used a resistor divider.

 

[tmchen00]

When use MOS device, be careful that
W1/W2 is in inverse proportion to (Vgs-Vt)^2,
not (Vgs)^2.

 

[jordan76]

Hi Fom,

You are absolutely right in saying that resistor divider will have better performance. But you know, the big area penalty for big resistor,uh-ha? :wink: So if the requirement is not too high and the performance is acceptable, it is ok to use transistor divider.

Hi v_naren.

As the figure shows,PMOS is diode connection which means the drain is connected to its gate . Don't you think so? :wink:

regards,
jordan76

 

[ablue]

When use PMOS as voltage divider, pay attention that PMOS cannot match each other because they are in their own well.

If you need high performance, you'd better use Resistor

 

[electronrancher]

i suggest using resistors instead of transistor voltage divider for a few reasons.

1) Vth mismatch - even for large devices you will get a few mV of Vth mismatch. This will be amplified by the loop gain of the circuit (M1 is in loop, so it will null out, but M2 is outside of loop, so as the loop servos to adjust to M1, M2 will cause more and more error.)

2) In order to get a transistor to act like a resistor, you need to be deep in triode (subthreshold). This means W/L ratios of 0.1 or smaller - for matching of 1% use Total area >100um^2 with 150nm Tox. That means somewhere around 3/33 W/L, but then you need to bias the gates at the proper potential - using them like diodes as shown above will make them act like diodes, not resistors.

3) Tempco - Vth changes with temp, and unless you split the wells (area penalty) you will get temperature drift.

4) As you take current away from the M1/M2 string, the biasing of the gates changes, which is why your ouptut goes up with load. Actually, I can't think of a good way to get a diode to act like a resistor. You'd need to connect the gate of M1 to -Vth and the gate of M2 to -2Vth-Vdsat in order to get them to act like resistors, but you don't have a negative supply..

I would really suggest resistors. If your amp can't drive the resistors directly, use an NMOS follower for easy compensation, or a PMOS common-source for low dropout.

 

[wolf001]

I have designed a bipolar one.I used resistor to be voltage divider.

 

[surianova]

M1 and M2 are both PMOS whose substrate should be connected to their source respectively to eliminate body effect.

Please correct me if I am wrong.

regards,
jordan76

For Pmos diode connected resistor, gate should connect to drain and the bulk should connect the highest potential node, that is source. If you connect bulk to drain( low potential), it will cause reverse bias( current will flow from drain to bulk and cause short circuit.

Normally for this kind of feedback, it is better to use pure resistor, it will be more stable because the active resistor will change its value according to its vgs and vds as well. So, using active resistor is not encourge.

 

[jordan76]

surianova,

For the former part, I totally agree with you. I do not see any difference between us.

For the latter part, it also depends on the tradeoff between application requirement and area/cost. Using pure resistor will cause big area overhead for generic CMOS process to keep the current small enough.

regards,
jordan76

 

[JPR]

First, gm of the transistor is a small signal effect, while the gain you are trying to get is a large-signal effect, which MAY or MAY NOT equate well to gm.

Second, the current in the feedback divider will be VERY temperature and process dependant. Be very careful that the current is not too much or too little at the process and temperature corners.

Because of these things, I would also recommend a resistor divider, if the space permits. Other options that may be better would be a switched capacitor feedback circuit or a switched capacitor gain stage after the bandgap, followed by a unity gain buffer. If the bandgap is not feeding any other circuits with 1.22V, you may be able to use a different bandgap design to obtain the 2.1V directly, or possibly design a bandgap that would give outputs at both 1.22V and 2.1V, especially if the 2.1V can be allowed to vary with temperature (as would surely be seen with the MOS resistors as feedback)

 

[amraldo]

u r using nmos transistors(not pmos) as diode connected for voltage division & here is my notices:
1-a diode connected has the gate connected to the drain & not to the source as u did.
2-the upper one suffers from the bulk effect. u must tie its bulk to the ground.
3-ur operation is steady state & it's circuit gain = 1+R2/R1

 

[electronrancher]

just one note on #2 above - you tie bulk to source to AVOID body effect. tying bulk to the rail will cause body effect in this transistor. remember, you calculate with vbs - voltage from body to source