Balanced NMOS Voltage Controlled Oscillator

[NIALA]

hi,

I am in the process of designing a DPLL through cadence(180nm process) . I completed a 200mHz center frequency VCO for a PLL using a current starved oscillator. Now i am trying to design a DPLL based on a 2.4GHZ balanced NMOS VCO. So far i wasnt able to generate any oscillation and i am starting to think that i am missing something in the concept.


Does any one have materials or tutorial in the design of a VCO based on a balanced NMOS configuration..

It will be really appreciated thanks!!!!

 

[erikl]

... materials or tutorial in the design of a VCO

Don't know if this can be helpful:

View attachment VCO_workshop_instruction.pdf
View attachment VCO_workshop.zip

 

[NIALA]

thanks for your help!!!!!

 

[NIALA]

thanks erikl your pdf file was really helpfull !!!!! Il learned how to use the PSS analysis to characterise a VCO... thanks a lot