bais circuit oscillation

[d_zhi]

explain bais

Help!

I used a bias circuit as below, and found some oscillation. Rb is off-chip, so I can see Vb-voltage drop on Rb oscillating between 0 and some value. The oscillation frequency is related to stray capacitance at the pin connecting Rb. And this oscillation can be seen in HSPICE simulation as well.

How to fix it while keeping Rb off-chip?

 

[tsanlee]

resistor bais circuit

Help!

I used a bias circuit as below, and found some oscillation. Rb is off-chip, so I can see Vb-voltage drop on Rb oscillating between 0 and some value. The oscillation frequency is related to stray capacitance at the pin connecting Rb. And this oscillation can be seen in HSPICE simulation as well.

How to fix it while keeping Rb off-chip?

You can check these items.
1.Add some compensation cap in bias circuit,and reduce B.W. of BIAS
Rb is off-chip, and it will induce some parasitical inductor and cap from I/O pad and bonding wire.
2.check you self-bias MOS
3.what process do you have?
Do you have p-well and n-well in a process ?

 

[d_zhi]

[quote="tsanlee]
You can check these items.
1.Add some compensation cap in bias circuit,and reduce B.W. of BIAS
Rb is off-chip, and it will induce some parasitical inductor and cap from I/O pad and bonding wire.
2.check you self-bias MOS
3.what process do you have?
Do you have p-well and n-well in a process ?[/quote]

Thanks, Tsanlee,
I fogot to show the startup circuit in the schem. The bias circuit has two stable points: Ib=0, and Ib=f(Rb). From the simulation, it looks like if parasitical cap is over ~1pF, the bias circuit tends to stablized @ Ib=0, which activate the startup circuit. And then it goes in this circle. When I use a oscilloscope to measure Vb, the probe will introduce 8pF cap, so I can see the oscillation.

I only got n-well. Could you please explain in a little bit more detail on how to analyze B.W. of bias circuit?

 

[tsanlee]

[quote="tsanlee]
You can check these items.
1.Add some compensation cap in bias circuit,and reduce B.W. of BIAS
Rb is off-chip, and it will induce some parasitical inductor and cap from I/O pad and bonding wire.
2.check you self-bias MOS
3.what process do you have?
Do you have p-well and n-well in a process ?

Thanks, Tsanlee,
I fogot to show the startup circuit in the schem. The bias circuit has two stable points: Ib=0, and Ib=f(Rb). From the simulation, it looks like if parasitical cap is over ~1pF, the bias circuit tends to stablized @ Ib=0, which activate the startup circuit. And then it goes in this circle. When I use a oscilloscope to measure Vb, the probe will introduce 8pF cap, so I can see the oscillation.

I only got n-well. Could you please explain in a little bit more detail on how to analyze B.W. of bias circuit?[/quote]


1.The bulk of NMOS in P-sub N-Well Process ,it can link to vss(not source )
2.The gate of M17 link to BIASN
the V(CASN) maybe come form strat up circuit,not bias circuit.
3.Can you caeck the gate of M15 M16 in these condition.
I guess taht the start up circuit failure.
4.The satbility of this circuit , I often use the step response .
Measure the B.W. of this circuit is so difficult.
We often add some compensation cap to reduce B.W. We use this circuit to provide a stable bias current.

 

[marshel]

for ac simulation

This circuit is quite the same as the figure described in <analog integrated circuit design> by david johns and Ken Martin, page 259.
What is the stray capacitance valute you added?

Added after 17 minutes:

I think you can add a cap about 5pf between the drain of M9 and VDD, I have seen a lot of bias generation with this cap. In my simulation I really find this cap help to stable the circuit.

Added after 29 minutes:

For stability analysis, I think you can do the ac analysis shown in the attachment.
V1 should have a 180 phase shift from the singal added in the gate of P0, if the phase shift>360 degree and still have gain>1, the circuit will oscillate.

 

[d_zhi]

Re: for ac simulation

This circuit is quite the same as the figure described in <analog integrated circuit design> by david johns and Ken Martin, page 259.
What is the stray capacitance valute you added?

Added after 17 minutes:

I think you can add a cap about 5pf between the drain of M9 and VDD, I have seen a lot of bias generation with this cap. In my simulation I really find this cap help to stable the circuit.

Added after 29 minutes:

For stability analysis, I think you can do the ac analysis shown in the attachment.
V1 should have a 180 phase shift from the singal added in the gate of P0, if the phase shift>360 degree and still have gain>1, the circuit will oscillate.

Yes, it is from the <analog integrated circuit design> by david johns and Ken Martin. Just making some changes on transistor dimensions. I tried it before using on-chip resistor. No oscillation. So never thought it could be a pro.

For the stray cap, I poured grn around the pin, so it might be ~pF. And when I made the test by oscilloscope, the probe itself introduce 8pF. plus bonding, packaging I guess it is more than 10pF.

Thanks guys, I will try adding some cap, this really helped.

 

[paschosz]

Message is unavailable.

 

[pfd001]

This circuit will oscillate when the off chip cap is large. You can compensate it with on chip cap at the node BIASN. Add a cap between BIASN and gnd will help you to get enough phase margin

 

[yorande]

Hi, would you please explain why could an off chip large cap cause oscillation?
It happened when I add an extra large like 100uF cap to the VDD of an amplifier.

 

[leo_o2]

What happens if 1uF external cap is added.

 

[yorande]

Well, it oscillate at smaller gain with 100uF.
With 1uF, it oscillates too, but the oscillation happens at higher gain.
Seems there must be a optimum cap value.
But I haven't found it.
But why should this happen??
I think caps are for filtering and are good for stability.