[SOLVED] Bad synchronous description error VHDL

I am new to VHDL. Infact, this is my first attempt at writing a code. I wrote the following code for the downsampling of an image in VHDL.

entity downsampling is
Port ( clk : in STD_LOGIC;
din_ip : in STD_LOGIC_VECTOR (9 downto 0);
we_ip : inout STD_LOGIC_VECTOR (0 downto 0);
addr_ip : inout STD_LOGIC_VECTOR (3 downto 0);
dout_op : out STD_LOGIC_VECTOR (9 downto 0)
);
end downsampling;

architecture Behavioral of downsampling is

COMPONENT blk_mem_gen_v6_3
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;

COMPONENT dwnsmpl_bram
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;

signal sig_we_ip : std_logic_vector(0 downto 0) := "1";
signal sig_we_op : std_logic_vector(0 downto 0) := "0";
signal sig_en_op : std_logic;
signal sig_dout_ip : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
signal sig_addr_ip : std_logic_vector (3 downto 0) := "0000";
signal sig_addr_op : std_logic_vector (2 downto 0) := "000";

begin

sig_we_ip <= we_ip;
sig_addr_ip <= addr_ip;



ip_img : blk_mem_gen_v6_3
PORT MAP (
clka => clk,
wea => sig_we_ip,
addra => sig_addr_ip,
dina => din_ip,
douta => sig_dout_ip
);

op_img : dwnsmpl_bram
PORT MAP (
clka => clk,
wea => sig_we_op,
ena => sig_en_op,
addra => sig_addr_op,
dina => sig_dout_ip,
douta => dout_op
);


process(clk) -- din_ip, addr_ip, we_ip=1 then clk

variable count_ip: integer range 0 to 16 := 0;
variable count_op: integer range 0 to 16 := 0;

begin

if(rising_edge(clk)) then -- if rising edge => write and increment count
if(sig_we_ip="1") then
if(count_ip<16) then -- count=1 for first write, count =16 for 16 writes
count_ip:=count_ip+1;
end if;
end if;
elsif(falling_edge(clk)) then -- if falling edge => chng addr_ip , din_ip changes at falling edge
if(sig_we_ip="1") then
if(count_ip=0) then -- if falling edge bfr rising => do nothing

elsif(count_ip<16) then
sig_addr_ip <= sig_addr_ip + "0001";
elsif(count_ip=16) then
sig_addr_ip <= "0000";
sig_we_ip <= "0";
end if;
end if;
end if;

--write cycle finished--write cycle finished--write cycle finished--write cycle finished

if(count_ip=16) then --enable op_img
sig_en_op <= '1';
sig_we_op <= "1";

if(rising_edge(clk)) then
if(sig_we_op="1") then
count_op := count_op + 1;
end if;

elsif(falling_edge(clk)) then
if(count_op=0) then

elsif(count_op<8) then
sig_addr_ip <= sig_addr_ip + "0010";
sig_addr_op <= sig_addr_op + "001";
elsif(count_op=8) then
sig_en_op <= '0';
sig_we_op <= "0";
end if;
end if;
end if;

end process;
end Behavioral;

-------------------------------------------------------------------------------------------------

The image is stored in a BlockRam. After synthesising i got the following error:
"line 99: Signal sig_en_op cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

Can someone point out the mistake??? Thank you.

Whoaaaa, that's the least of your problems. First of all, you can only have one clock statement inside a process, you've got at least four that I could see. It would help a lot if you indent your code so we can see where your IF statements begin and end, and use the CODE tags around your posted code (the "#" symbol in the toolbar above the text area).

Although you CAN put multiple signal assignments inside a single process, what you have might be a little clearer if you had separate processes for different signals, i.e., sig_en_op can be in a separate process from others. Then you've got sig_addr_ip assigned both inside and outside the process, that will give you an error for sure.

There are just too many other errors here; you need to step back a bit and think about what you are really trying to do. Think about the hardware you are trying to describe.

I think maybe you should start with something simpler than image processing for a first VHDL project.