AXI WR and RD channels access same address simultaneously

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gari93

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Hi,

I have a doubt regarding the independance of AXI WR and RD channels. Does it mean that a master can launch a wr access and a rd access simultaneously.
If this is the case, then what happens when the address is same for RD and WR address channels.
 

The master should issue write transaction first then the read transaction otherwise it can be said which instruction will be served first. it will depend upon interface and qos service value. and result will be unpredictable. if I am wrong plz make me correct

Thanks and regards
Vir_1602
 

Thanks for answering.

still i have a doubt, when one master is accessing a slave and wants to perform write txn to address location 'hxxxx and some other master wants to perform read txn to same slave's location. Then what will be the read value for read transaction?? Both read and write transaction performs simultaneously.

thanks in adv.
 


If multiple masters are there, then there will be a AXI bridge, and which will take care these traffics.
IF two masters are accessing the same slave, then the bridge will give grant to the highest priority master and after that the 2nd master can transfer. (it can be also round robin).
The bridge will allow only one master to access a single slave.
All this is depends up on the implementation of bridge.
 
Thanks,

when a master performs a read from a slave's memory location which is empty(i.e. no master has written to that slave's memory location previously), then what will be the value of data as a result of that read?
Will the slave wait till some master has written a value to that location??
 

A memory location can never be empty...The location will have a value, it will contain a random value from power up.
 

and as we reset the system first it will definitely contain some known value
 

Not if it is a really a memory. Can't think of any memories that have resets, that will reset the memory array cells. You have to write to them to have them "reset", otherwise you'll read out whatever random values that the cells initialize to at power up.
 

This has also been a question of mine. IIRC, there are some priority and scheduling features from some of the extra AXI signals (eg, not the data/addr/response signals). For memory, you would want to ensure coherency for reading back just-written data, but you would also like to issue reads before writes if they don't conflict. That way, the read latency is reduced and you can continue processing.
 
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