AXI Interconnect IP core from Xilinx Coregen or Synopsys DesignWare

For the more experienced SoC designers...

I need to implement an AXI interconnect which will support AXI4 and AXI4Lite. The AXI environment should be multi-master and multi-slave. The question is which one to get.

1> Xilinx Coregen can generate one for you. The following excerpt is directly from the spec, ds768_axi_interconnect.pdf - "The AXI Interconnect core is provided as a non-encrypted, non-licensed (free) processor core (pcore) in the Xilinx® Platform Studio (XPS) software. The core is also provided in the ISE® Design Suite for use in non-embedded designs via the CORE Generator™ tool flow."

2> I also have access to Synopsys DesignWare Library from which the AXI Interconnect IP should be possible to download (didn't check as of now, but making an educated guess).

3> Build my own

So which one is recommended?

You can't legally us the Xilinx IP in anything, but a Xilinx part. Just read the header in the files generated.

If you have access to the DW component then why would you want to build your own. Spend the time it would take to make your own homegrown AXI on improving the rest of the design.