bens
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AXI 3 (or 4) specifies that "There must be no combinatorial paths between input and output signals on both master and slave interfaces."
Now, I can read this in two ways:
1. There must be no combinatorial paths between input and output signals and also between output and input signals on both master and slave interfaces.
2. There must be no combinatorial paths between input and output signals ,but there can be between output and input signals on both master and slave interfaces.
I'm thinking it's probably the first since the reason for this has got to be timing, but I'd appreciate your input
Now, I can read this in two ways:
1. There must be no combinatorial paths between input and output signals and also between output and input signals on both master and slave interfaces.
2. There must be no combinatorial paths between input and output signals ,but there can be between output and input signals on both master and slave interfaces.
I'm thinking it's probably the first since the reason for this has got to be timing, but I'd appreciate your input