awready and wready arready signals are default 1?

[coshy]

Hi.

Do awready and wready arready signals assert high when I don't give any signal to slave except clock and reset?

Do those signals have 1 default value?
In my case, those signals are asserted after reset.

Does anyone know what it is happening? Is this normal protocol? When I check the specification,there is asserted by master signal. But my case someting weired.

 

[dpaul]

As per AMBA:
The default state of AWREADY can be either HIGH or LOW. This specification recommends a default state of
HIGH. When AWREADY is HIGH the slave must be able to accept any valid address that is presented to it.
This specification does not recommend a default AWREADY state of LOW, because it forces the transfer to take at least two cycles, one to assert AWVALID and another to assert AWREADY.

The default state of WREADY can be HIGH, but only if the slave can always accept write data in a single cycle.

Do those signals have 1 default value?

Hence as per my understanding of the spec, they can have 1 or 0. Depends on how the AXI i/f for the slave has been designed.

Does anyone know what it is happening? Is this normal protocol?

Read the spec carefully.

When I check the specification,there is asserted by master signal. But my case someting weired.

Really? In the spec IHI0022E, it says that slave is the source for both awready and wready.