twb8t5
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I would like to OR more than two signals.
I read that writing:
out <= in1 OR in2 OR in3 OR in4 OR in5;
or
FOR i IN range LOOP
out := out OR in(i);
END LOOP;
might create a cascaded structure like:
(.|.)|.)|.) instead of (.|.)|(.|.) or better (.|.|.|.)
How do I avoid this or can it not happen?
For an FPGA with LUT4 the realization might ideally be (.|.|.|.)|(.|.|.|.)|(.|.|.|.)|(.|.|.|.)
But I wish to write code that is device independent.
Similar Thread: https://www.edaboard.com/threads/238870/
Index: multi input gate
I read that writing:
out <= in1 OR in2 OR in3 OR in4 OR in5;
or
FOR i IN range LOOP
out := out OR in(i);
END LOOP;
might create a cascaded structure like:
(.|.)|.)|.) instead of (.|.)|(.|.) or better (.|.|.|.)
How do I avoid this or can it not happen?
For an FPGA with LUT4 the realization might ideally be (.|.|.|.)|(.|.|.|.)|(.|.|.|.)|(.|.|.|.)
But I wish to write code that is device independent.
Similar Thread: https://www.edaboard.com/threads/238870/
Index: multi input gate