Avoiding bypass capacitors

Hi,

it's like driving with tires without profile. "Functionally" you can drive, but it´s more risky. More risky off road or at rain or with high speed. A potential risk for random malfunction. And a risk for increased EMI/EMC problems.

Without capacitors - no matter how wide your traces are - you have a series impedance. And every signal transition within your IC causes a current spike. Multiply this current spike with the external impedance than you get a voltage (drop) spike. During operation there will be more or less parallel signal transitions causing more or less voltage drop.
And in worst case the combination of signal transitions is high enough for the voltage to drop to cause malfunction. Maybe there is no problem at all, maybe it fails after a year, maybe after a second.

If you do an eye diagram you will see some transitions are more delayed, or with less dV/dt, the eye becomes smaller, the signal quality becomes worse.

I guess the 2.2uF is less critical than the 100nF. But in detail it depends on your signals and your PCB layout. If you have a true power plane (and GND plane) with less than 3mm (including via) to the supply pin for the 1.2V supply then it´s less risky than with power supply traces.

You may show your PCB layout for more detailed answers.

It´s like with the tyres. As long as you know what you are doing, as long as you know where and when it becomes critical, when you know where and how you have to measure your safety margin ... you may do it.
If you are a race car driver you learn (experience) how it feels to loose grip, you learn how to react in this case.

Especially for a newbies it´s far more "safe" to use the capacitors, to use a power plane, to use a GND plane. A 4 layer PCB compared to a 2 layer PCB is so much easier and gives so much more functional reliability.

Klaus

The 1.2V node is powered by an internal voltage regulator. Worst case it becomes unstable under certain conditions (PVT variations, chip activity) without the designed capacitors.

Using a DSO, set it up for infinite persistence, and look at those pins for
extended time, minutes to an hour or so, with board actively in traffic
condition. That will capture the majority of transient conditions the chip has
to power and show you how low the Vdd pin drops in worst case. If thats
out of spec you have your answer. Be careful about probing, placement of
ground probe lead as close to chip Vss pin(s) as possible. Maybe tack a pin
at site for ground clip to attach. If you set it up for color graduated

I would use auto sweep mode, max sampling rate, peak detect mode. If scope
has it color graduated mode to see freq of occurrence between various triggers.



Then do it again for level triggered, set for < min val you say in first acquisition,
to see details of out of spec low transients.

This is not a perfect investigation tool, but should reveal a lot.

If you do not have a DSO build a comparator, construction Manhattan style, right
on top of chip, set its trip to Vdd min, and see if you get any scope triggers that way.
You could add a F-F to it to create a led trig light occured indicator.

Note not all bulk caps have equal performance in bypass applications, polymer tants
best in class(next to MLCC) :






Regards, Dana.

As an example, I once forgot to put a 4u7 capacitor on the input of a DC/DC converter and when I probed the 3v3 input line it was EXTREMELY noisy, which in all fairness is expected on such a switching converter that is chopping up the input, and quickly changing the load on that 3v3 line to convert down to a 1v8 output.

Adding in the 4u7 capacitor after I noticed the issue instantly cleaned up the 3v3 rail and I had no issues going forward.

Moral of the story, just install the capacitor, don't risk running without it as it could result in all sorts of funny issues happening.