Sep 24, 2009 #1 C cafukarfoo Full Member level 3 Joined Jul 25, 2007 Messages 170 Helped 8 Reputation 16 Reaction score 5 Trophy points 1,298 Activity points 2,510 Hi Sir/Madam, Can someone share their method to avoid reg/wire bus optimization during FPGA synthesis? I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/Chipscope software. Thanks in advance for your help.
Hi Sir/Madam, Can someone share their method to avoid reg/wire bus optimization during FPGA synthesis? I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/Chipscope software. Thanks in advance for your help.
Sep 24, 2009 #2 J j_andr Full Member level 4 Joined Mar 30, 2008 Messages 207 Helped 59 Reputation 118 Reaction score 37 Trophy points 1,308 Location europe Activity points 2,491 verilog: wire xxx /* synthesis syn_keep */; reg yyy /* synthesis syn_preserve */; somehow similar in vhdl; ---
verilog: wire xxx /* synthesis syn_keep */; reg yyy /* synthesis syn_preserve */; somehow similar in vhdl; ---