Avoid reg/wire optimization in FPGA synthesis

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cafukarfoo

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Hi Sir/Madam,

Can someone share their method to avoid
reg/wire bus optimization during FPGA synthesis?

I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/Chipscope software.

Thanks in advance for your help.
 

verilog:
wire xxx /* synthesis syn_keep */;
reg yyy /* synthesis syn_preserve */;

somehow similar in vhdl;
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