avoid a zero using cascode compensation ??

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cmos_ajay

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Attached is a folded cascode amplifier with a cascode compensation capacitors Cc.
How does this circuit prevent the formation of the undesired zero (in the right half of the s-plane ) ?

Please let me know a logical explanation .
 

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In classical compensation the Cc is a short circuit for high frequencies, so You inject signal in opposite phase to the output by Cc, producing RHP zero.

In cascode compensation Cc is buffered by CG amplifier, so it lies on virtual ground preventing the above situation.
Unfortunately cascode compensation provides three poles and two zeros and for newbies could provide transfer function with high Q pole seriously degrades stability (high freq. peak in magnitude).

All aspects You have explained in classic papers from Gray, Ahuja, Ribner & Copeland and Fisher (all IEEE SSC 1981-1985)
 
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    erikl

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**In cascode compensation Cc is buffered by CG amplifier, so it lies on virtual ground preventing the above situation.
Can you explain this sentence in more detail so that I can visualize it clearly ??
Thanks.
 

Gray and Meyer tutorial about CMOS OPAMPs - section IV mentioned about Ahuja and independly Read and Wieser idea.
Ahuja first implementation of cascode compensation by using current buffer in compensation path in "standard" two stage opamp. At the page 3 You have a small signall scheme.
Copeland and Ribner implementation for opamp with cascode first stage
Fisher - last "classic" paper about cascode compensation.
 
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