Avalon MM (master) to AMBA APB (Slave ) Interface (Need VHDL Code or Guidance)

Hi,

I need to write an interface(bridge) between the Avalon MM and APB bus. I have the follwoing signals

Avalon MM (Master) APB (Slave)
------------------- ---------------
Clk ---->
Reset ---->
(32) Address ---> PADDR -----> (16)
Write ---> PWRITE
Read --->
(32) WData ----> PWDATA ---> (32)
(32) RData <---- PRDATA <---- (32)
Wait <---- PRREADY <-----
Valid <---- PSLVERR <-----

Could someone please help me on what will go into the architecture (VHDL ) code here ?
Any examples would help me........

Thanks
- Sharon

This might help you as Qsys interconnect supports both interface standards.
https://www.altera.com/literature/hb/qts/qsys_interconnect.pdf

Thanks, but I was looking for an example for guidance.

You can write a state machine to control the communication between these two interfaces.

In the architecture include a clocked process and another process where you write your bridge or wrapper logic.