[SOLVED] Avalanche pulse peak holding circuit

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Hello everyone, I am interested in avalanche transistor based high voltage pulse generator. A few nanoseconds after you put the avalanche transistors into avalanche mode, they go back to their original state. But I want at least 0.5 us pulse width. After doing a general research, I saw 2 different opinions on this subject, but I still did not fully understand the logic.
1) Trig voltage shaper and phase delay
2)Recovery time
My goal is to hold the high voltage for 0.5 us. What are your suggestions for this?
I also share the ltspice file of the single transistor circuit.
 

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--- Updated ---

Would it be safe to say what you care about is a fast edge and then some fixed
minimum width ?


Regards, Dana.
 
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At that kind of pulse width you're well within the
switching regime of GaN FETs (seen designs down
to ~ 10ns FWHM) and timer ICs. It'd be cheap and
easy to build a 74AC123, 74AC04, EPC or GaN
Systems FET (depending on what kind of packaging
you like to work with) and figure out your isolation
(presuming you want a positive HV rail, and a ground
referred trigger).

You could use a single lithium cell for the gate drive
and a pulse xfmr for the '123 trigger perhaps, or a
fast opto, or a more modern isolator if you like
depending on what you might expect or desire for
common mode dV/dt.
 

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a pulse shaping network ( L's & C's ) is required for 500nS, also avalanche not required for this speed, could be done with SiC mosfets and a transformer and good gate drive.
 

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I need less than 5 nanoseconds rise time and high voltage pulse. For this, I use an avalanche transistor based marx generator. There are ready-made products based on avalanche transistors, so there are those who do it. But they have a pulse width close to 1 microsecond, I wonder how this is done. They probably manage to keep the transistor on after the transistor goes into avalanche mode. Delaying the trig voltage and changing the waveform, which I have seen in some articles, but I did not understand the logic of this.
--- Updated ---

danadakk said:
minimum width
Click to expand...
No, about 1 us or 0.5 us
danadakk said:
fast edge
Click to expand...
Yes trise<5ns
 

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Avalanche transistor rating show as a relation between switching current and pulse width, you can e.g. review Zetex datasheets. 500 ns pulse width doesn't allow useful pulse currents, presumed you are driving a resistive load.

Charging/discharging a capacitive load might work because you have high currents only during edges.

Quite generally I agree with Easy peasy that you should try to use a recent switching technology for your pulse generator. Avalanche switchers have been rarely used in new applications during the last 40 years due to availiability of fast HV MOSFET.
 
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Thank you for your answers. First of all, my load is capacitive. I have studied mosfet based designs but my research location is avalanche transistor based avalanche pulser. I am sharing you a graphic of a product that works with the same logic. When I increase the capacity of the output load, I increase the fall time of the output voltage, but I cannot keep it constant and I am looking for a way.
 

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The only way to reduce the fall time is to short out the line after the required pulse width, e.g. 1700V SiC mosfet,

please show your full ckt for better answers
 
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