[SOLVED] Automating RTL simulation using VCS of Synopsys

Hi all,

I have various test-cases to be run on RTL simulation. These test-cases are in the form of HEX files, e.g. nc_program.hex My top level test-bench loads data from this .hex file to the internal memory and then the simulation/execution proceeds.
Up to now I have been doing this manually, changing the nc_program.hex file every time, and then launching ./simv -gui (in this case I supply a "run XYms" command at the dve> prompt ) or just ./simv (in this I wait till the simu completes and then exit it by hitting Ctrl+Z).

Now I want to automate the process of testing and want to write shell script for it (a Makefile will also be ok). But the bigger questions for me is...
1> how can I determine when VCS has completed simulation successfully (when I don't have visual indication)?
2> how can I record the sim o/p (record o/p of the transcript window)?
3> if i want to run it for some XYms, how do I pass that option to simv, possible ? If it is not possible the I can just run ./simv, but then how to catch the event that simulation is over?

Please give me hints, indications for doing this automation.
I have not read the VCS manual, so if this info is there please inform me.

Thanks,
dpaul

using dc-compiler for synthesis you can happily write a make file. for your first question whenever your simulation got completed it will generate a batch mode result.with those results you can verify whether you are getting correct o/p's or not, without going for dve & and dve wv for w/v forms for your design.

Sorry anusha vasanta, I can no way figure out how you reply fits to my thread!

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Hi,
I have done the complete automation using Python script (way powerful, feature rich and flexible than shell script). Now for the benefit of others I will very briefly answer my own questions as to how I had solved them.

1> how can I determine when VCS has completed simulation successfully (when I don't have visual indication)?
Ans: There are two ways -
a> One can use a do file in which you specify the simulation run time. The following command can be used to launch, run and exit VCS Synopsys RTL simulation for a specified duration.
./simv -ucli -do dofile-name.do
b> Smarter way is to check for a condition in the top-level test-bench that ensures your simulation is finished and then if the condition is encountered issue a $finish statement. I have used this option as it reduces the dependency on do files (I have many different test-cases and creating a do file for each sim run was not good practice).

2> how can I record the sim o/p (record o/p of the transcript window)?
Ans: I am sure google has the answer when you are writing a shell script.
As I was using Python, I used "commands.getstatusoutput(./simv)[1]". There is a nice thread on 'stackoverflow' for this. You can then use the logging.info() to put the above output to a log file.

3> if i want to run it for some XYms, how do I pass that option to simv, possible ? If it is not possible the I can just run ./simv, but then how to catch the event that simulation is over?
Ans: Already answered in <1>.

Hope this helps.