Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Automatic gain controller action

Status
Not open for further replies.

paulmdrdo

Full Member level 3
Full Member level 3
Joined
Jan 17, 2014
Messages
183
Helped
1
Reputation
2
Reaction score
2
Trophy points
18
Activity points
1,394
Can you guys explain to me how the turning on of Q2 and the charging of C2 increases the vgs of the FET? An equation would be helpful.

1592643088916.png

paste-e096893bb4ab68a05aafda4a57d46e34fb13494e.png
 

Huh, does not seem to show on my PC, I see no attachment.....


Regards, Dana.
 

The B-E junction of Q2 is critical here, with zero bias it works rather like a diode to rectify the signal passing through C1.
As Q2 conducts it bring the top end of R5/C2 nearer to ground potential so Q1 conducts more and makes the bottom end of the potential divider R3/Q1 Rds drop the signal to the IC. Note that Q1 must be a JFET for this to work, in other words it is more conductive between drain and source when there is no Vgs and it's effective resistance increases as the gate is made more negative with respect to its source pin.

Brian.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top