Automatic Gain Control Stage

[archiees]

I found this attached schematic as part of an oscillator circuit. It is supposed to be an AGC stage in which V3 is a portion of the ac output of the oscillator (through inductive coupling) which is being fed to the AGC. The output of the opamp controls some bias voltage which controls the amplitude of the oscillations. What i dont understand is, how by varrying the dc value of V2 voltage source we can control the output of the opamp and hence the bias of the transistor in oscillator.
So, the voltage after the R6 is fed to the transistor bias in the main oscillator circuit.
Explaination of the circuit will help me a lot. thanks

 

[flatulent]

V2 sets the neutral point of the amplifier input. When the noninverting input goes higher than the voltage on the noninverting input, the amplifier output goes positive. When it is less, the output tries to go negative.

 

[Borber]

Rectified portion of oscillator voltage at noninverting input must be equal to V2 for oscillator to acheive vanted amplitude. If V3 is lower than what is preset by V2 output of OP AMP goes negative regarding to neutral point and thus via bias circuit of oscillator increases the amplitude of oscillations and viceversa.

 

[Btrend]

the retified stage also form a peak detector
and the next stage is a active LPF with DC gain = (1+R5/R4) and pole at 1/(R5*C3).
The scenario like this: the amplitude of positive half is sensed and then compared with V2 and then only average signal (LPF) is extracted to the output to tuned ur bias current of oscillator.