Audio Sigma-delta ADC

[winsonpku]

how do you define number of bits sigma delta

Please help to recommend some good papers which are focused on audio sigma-delta ADC. Especially the architecture is good and has been verified by you. Thanks!

 

[courcirc8]

low power audio sigma delta

I strongly recommend you to try the excellent R. Schreier mathlab toolbox to studdy the modulator order.
https://www.mathworks.com/matlabcentral/fileexchange/19
There is no absolute answer, it depends on.
- your specifications
- the available clock (OSR, jitter)
- the power consumption allowed
- knowledge on mismatch-shaping algorithms
- ...

Most of the converter published recently uses CT modulators, but in that case, you need to have a clean clock to avoid designing a switched-cap DAC.
Avoid low order modulator with a low number of bits inside the quantizer, or you will face tone problems (limit cycles)

 

[winsonpku]

sigma delta stability

I think you are right. The analog design is just a trade-off and no the absolute best solution.
I have dowloaded the toolbox and will try to stuty this one.
In fact, my ADC is used in TV audio, such as recording. The power consumption is not so tough.
Would you give some advice? Thanks!

I strongly recommend you to try the excellent R. Schreier mathlab toolbox to studdy the modulator order.
https://www.mathworks.com/matlabcentral/fileexchange/19
There is no absolute answer, it depends on.
- your specifications
- the available clock (OSR, jitter)
- the power consumption allowed
- knowledge on mismatch-shaping algorithms
- ...

Most of the converter published recently uses CT modulators, but in that case, you need to have a clean clock to avoid designing a switched-cap DAC.
Avoid low order modulator with a low number of bits inside the quantizer, or you will face tone problems (limit cycles)

 

[courcirc8]

understanding sigma delta adc

You should tell also the available clock. It will define the maximum OSR you can use.
Many designer uses the second order single-loop structure because of its stability for a single-bit quantizer. I would not recommend it because it bigger susceptibility to tones problems.
Going to higher modulator order is not a big problem if you choose the feedforward compensation: a correct scaling of the integrator dynamic ranges is sufficient to solve the stability issue when the modulator is overloaded.

If you are familiar with switch-cap design and don't need any anti-aliasing, you can go safely for a DT modulator. There is a lot of litterature around this topics ...
You must have Schreier and Themes books:
https://www.amazon.com/Understanding-Delta-Sigma-Data-Converters-Schreier/dp/0471465852
https://www.amazon.com/Delta-Sigma-...10454/ref=pd_bxgy_b_img_c/176-7935734-9540327
You could use a third order multi-bit quantizer or a fourth order single-bit.

If you need some anti-aliasing, then there is a little bit more work to design a CT modulator, but don't forget it is more sensitive to clock jitter. Thw good point is that the complete modulator can be simulated with your favorite analog simulator ... within a night or two! (you will rely on your simulink model for the DT modulator)
Here is a very good reference for that:
https://www.amazon.com/Continuous-T...=sr_1_1?ie=UTF8&s=books&qid=1244492358&sr=1-1

Good luck with your design...