Attribution of pins when connecting FPGA and SDRAM

[telga]

FPGA and SDRAM

Hello,

I want to connect a SDRAM (single data rate) to a spartan 2e FPGA.
Are there some special recommendations about the attribution of the pins?

I saw, for example, the SDRAM clock coming from a FPGA standard IO pin, then return to a FPGA GCLK input.
What is the advantage of this solution ?

Thank you in advance

Telga

P.S. The FPGA case is a PQFP208 and the SDRAM case is a TSSOP56.

 

[cube007]

FPGA and SDRAM

Hello telga,

I don’t know a lot about the Xilinx FPGAs, but the devices are comparable with the Altera ones. For SDRAM signals Altera isn’t using special pins for data, address, etc. except for the clock! The clock is the most important signal when using synchronous RAMs. That’s why you have seen that the clock is feed back to the FPGA. I think that this design gives out the clock on a standard pin coming from a lock generator (Altera is using a PLL for doing this). The feedback is used for the SDRAM controller to setup and store all data, address, etc.

Did you check the Xilinx website for applications notes? Altera has a lot of them and I think Xilinx will give this information out too.

The easies way for would be to take some example designs and get the desired information from these.


Bye,
cube007

PS: Keep an eye on termination and dumping resistors for the SDRAM signals.

 

[telga]

Re: FPGA and SDRAM

Hi Cube007,

Thank you for your interest for my question.
I read the application note 134 and I also took a look on the XSA board from XESS.
What I search for is a design experience return.

For example, what is the best ground bounce workaround with PQFP208 cases ?

Telga

 

[kib]

Re: FPGA and SDRAM

the feedback clock is used for de-skewing the on-board clock skew.
u can check the user manual for spartan2e device.
u can find information on clock de-skewing using DCM

 

[shakalaka]

Re: FPGA and SDRAM

if you are using Xilinx FPGA...then you may also need to use...External PLL Circuitry to DeSkew...clock...etc....

 

[telga]

Re: FPGA and SDRAM

Hello shakalaka,

Can you explain me why ?

Telga

 

[shakalaka]

Re: FPGA and SDRAM

hey telga,
i want ot know your requirement and expectation.....
as Xilinx FPGA....have DLL instead of PLLs...and it is limited...
so you may want to have onboard deskew ciruitry...etc...