Hi Experts,
How to use the attributes of synthesis tool in our design
example
-- Xilinx specific clock buffer attributes
attribute buffer_type : string;
attribute buffer_type of accept_in_dec_s : signal is "BUFG";
attribute buffer_type of done_s : signal is "BUFG";
what is the purpose of using like this .some one explain me .
Basically you have to know, what it means to insert a BUFG primitive for a signal. As far as I see this is documented detailed in the common Xilinx manuals. But I'm not using Xilinx, perhaps a Xilinx user is motivated to explain.
BUFG is a xilinx primitive high-fanout buffer that connects signals to the global routing resources for low skew distribution of the signal.
BUFGs are typically used on clock nets as well other high fanout nets like sets/resets and clock enables.
You can refer to
doc\usenglish\books\docs\spartan3_hdl.pdf