sky_siliconthink
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Do you need an attractive VLSI/FPGA design project in your resume?
If yes, the 2D DMA controller project is a good choice.
It’ a rich feature 2D DMA controller with APB3+AXI4 interface. It’s specially designed for image/video application, while compatible with traditional 1D DMA controller. Here are the main features (should be competitive with DMA IP from ARM or Synopsys):
1) source/destination address can start from any byte location (no need 32bit aligned);
2) Support data copy of 2D window with data length in each dimension is [y_size, x_size];
3) Value range for x_size is [4, 65536];
4) Value range for y_size is [1, 65536];
5) There can be any number of byte gap after each line of x_size byte; And the gap for source/destination can be different;
6) Support scatter-gather mode (command linked list); Once started by SW, it can copy at most 256 blocks of 2D window;
7) Utilize some advanced feature to AXI bus protocol to improve data bandwidth: read cmd outstanding, read date out-of-order, concurrency of read/write on AXI interface;
You can enroll this course from this Udemy link: https://www.udemy.com/course/vlsifp...apbaxi-inf/?referralCode=DFE6AD483A9398E71B45
And there's special offer for early enrollment:
1~5 enrollment: 90% discount;
6~10 enrollment: 80% discount;
11~20 enrollment: 70% discount;
21~30 enrollment: 60% discount;
31~40 enrollment: 50% discount;
41~50 enrollment: 40% discount;
Please contact (write E-mail to siliconthink@126.com or short message in Udemy) the instructor for coupon of discount.
Wish you can find a decent job in VLSI/FPGA design.
If yes, the 2D DMA controller project is a good choice.
It’ a rich feature 2D DMA controller with APB3+AXI4 interface. It’s specially designed for image/video application, while compatible with traditional 1D DMA controller. Here are the main features (should be competitive with DMA IP from ARM or Synopsys):
1) source/destination address can start from any byte location (no need 32bit aligned);
2) Support data copy of 2D window with data length in each dimension is [y_size, x_size];
3) Value range for x_size is [4, 65536];
4) Value range for y_size is [1, 65536];
5) There can be any number of byte gap after each line of x_size byte; And the gap for source/destination can be different;
6) Support scatter-gather mode (command linked list); Once started by SW, it can copy at most 256 blocks of 2D window;
7) Utilize some advanced feature to AXI bus protocol to improve data bandwidth: read cmd outstanding, read date out-of-order, concurrency of read/write on AXI interface;
You can enroll this course from this Udemy link: https://www.udemy.com/course/vlsifp...apbaxi-inf/?referralCode=DFE6AD483A9398E71B45
And there's special offer for early enrollment:
1~5 enrollment: 90% discount;
6~10 enrollment: 80% discount;
11~20 enrollment: 70% discount;
21~30 enrollment: 60% discount;
31~40 enrollment: 50% discount;
41~50 enrollment: 40% discount;
Please contact (write E-mail to siliconthink@126.com or short message in Udemy) the instructor for coupon of discount.
Wish you can find a decent job in VLSI/FPGA design.