ATPG issue. Test patterns failed in simulation .

Hi Lee ,
The problem you are facing is a common problem .Some times the ATPG static simulation will pass & you will able to generate patterns .But same pattern simulation will fail in Verilog simulation , this could be because of your netlist library .There if you see there will path delay modelling specified in specify - end specify block .That can cause problem some times .

Only no-timing chk is not sufficient , have to take care of the unit delay .Which depends on the library .Try your VCS simulation using no-specify option .Even if its failing analyze ur simulation by picking the failing flop of the chains & chk if its failing during shift or capture .

I hope this gives some idea , how to debug .

Regards
Chandhramohan

Dear All :
I use the nospecify option , and simulation pass!

Thank you all for help me! Dear jackson_peng, Rameshs,Chandhramohanpeng, all of you are so nice, kind-hearted, patient , smart and experienced .
I am a newer , sorry for my silly question !
I thought if the timing define in specify block was zero, VCS will simulated with zero delay. I will study more about VCS later .
Thank you all again!

Best wishes
Leeguoxian

I still can't sovle it , can anyone help me , thanks.