ATPG issue. Test patterns failed in simulation .

[leeguoxian]

tetramax b7

Dear All:
I used TetraMax to generated the test patterns, but the test patterns failed in
simulation.
I have no idea how to find out the reason why it faided.
Can anyone help me?

There were N20 and N23 violations when I run TetraMax.
Need I fix them?
If I don't have to care about the N20/N23 violations, what should I do ?



Added after 1 hours 32 minutes:

More detail
1. My design used partial scan style
2. Pre layout netlist simulation passed
3. Post layout netlist simulation failed. ( Scan chains were reordered after P&R)
4. Both of the simulations without delay timing.

thx

 

[rameshsuthapalli]

tetramax set atpg

hello
i think u r problem is bcz of the violations present in the design after synthesis.make sure of those violations to be fixed before u run the simulation or plz run the simulations at no_delay mode of the nc verilog.
bye
rameshs

 

[leeguoxian]

sta pass simulation fails

hello
i think u r problem is bcz of the violations present in the design after synthesis.make sure of those violations to be fixed before u run the simulation or plz run the simulations at no_delay mode of the nc verilog.
bye
rameshs

Do u mean the violations present in TetraMax?
But pre-layout simulation was good, how could post-layout simulation failed?
I am so confused now !!!

 

[jackson_peng]

atpg fail

Since you didn't use delay annotate during both simulation, only the functionality are checked.

here i give my recommendation now.
1. don't doubt at the tools. however, you could use "check_dft" to help improve the scanability and coverage.

2. by checking your flow, you had scan-chain reordered during PR, so you should regenerate the ATPG pattern using post-layout netlist, and surely the old patterns wont be useful.

3. however, if you keep the scan-chain during PR, you can do one round formality between pre-layout netlist and post-layout netlist (note that the netlist should be forced to scan mode), which can help you check the functionality in short time.

regards.

 

[leeguoxian]

tetramax n20 error

2. by checking your flow, you had scan-chain reordered during PR, so you should regenerate the ATPG pattern using post-layout netlist, and surely the old patterns wont be useful.

Yes, I regenerated the Test pattern for the post-layout netlist,
but the simulations fail!

 

[jackson_peng]

c2 tetramax violation

well, that's all right.

then i suggest you to follow the third recommend to check whether your layout flow might violate the netlist.

 

[leeguoxian]

does atpg tools ignores multicycle paths

well, that's all right.

then i suggest you to follow the third recommend to check whether your layout flow might violate the netlist.

Dear jackson_peng:
I used check_test to check the post-layout netlist, and it could report the scan chain correctly. It seem there no scan structure errors in the post-layout netlist.

 

[jackson_peng]

spf all_bidirectionals

actually, check_test perform the DFT design rule check, rather than the chain order. and i wonder your PR flow would change the scan order, even thought that sound impossible.

usually, scan-chain is de-stitched and perserved before CTS&Routing, and re-stitched after optimization.

and i've not try other flows, so its beyond my experience to figure out where might be the problem.

regards.

 

[leeguoxian]

atpg simulations min

actually, check_test perform the DFT design rule check, rather than the chain order. and i wonder your PR flow would change the scan order, even thought that sound impossible.

usually, scan-chain is de-stitched and perserved before CTS&Routing, and re-stitched after optimization.

and i've not try other flows, so its beyond my experience to figure out where might be the problem.

regards.

Astro has the ability to reorder the scan chains with the files generated by DFT Compiler.
Do u think the order of scan chain will affect the simulation ?

 

[jackson_peng]

vcs 0-delay simulation tetramax patterns

scan chain can be and should be reordered after placement, which can significantly reduce the wiring length.
however, this step is usually performed in PC in general design flow, while the Astro which performs CTS & Routing, should perserve the chain order.

sure, the chain order will affact the ATPG test pattern, but not the simulation!!!


and buddy, actually, there're two points which i concern regarding your works, and either of them can cause the failure in simulation.
1. the correctness of your netlist, which you can do some functional simulation first, or do formality on the RTL and post-netlist in function mode.

2. the design flow, especially those steps in astro. which you have to maintain the chain order during CTS&Routing, and use formality to check the pre-netlist & post-netlist in scan mode.

Debug on ATPG simulation can be quite annoying, take it the last resort.

Regards.

Added after 3 minutes:

and if it is allowed, you can mail me the detail design flow you followed and the tools you used, from which i would know more on your design.
(by the way, i only familiar with the synopsys tools)

 

[rameshsuthapalli]

tetramax n23

hello all

i will explain what r the steps that we must follow in the pre and post layout simulation of the atpg.

1) we must generate the atpg vectors for the pre layoutnetlist. we will check those vectors in the simulation with the no delay mode of the ncverilog.
2)in the p&r section they will reorder the scan chain for the better roughtabulity .
3)after the P&R we must once again generate the ATPG vectors bcz already scan chain was reordered.
4) check those atpg vector with the p&R netlist with the max delay mode with the sdf annotaions.
5) check there is any vectors are failing. if verctor are failed the
check the STA with out the false paths and the multicycle paths.
so u will get the violations. so will know the path which is failing in the above simulations r equal to the path failed in the STA for same.so the violation occered is bcz of the false path present in the design . so scale down the frequency so that the scan STA hase no violations.
it will solve u r problem.
thanks
rameshs

 

[leeguoxian]

chain test pattern failed

My design Flow :

1. Insert partial scan chain with DFT compiler.
DFT Violations:
<1> Improperly driven three-state net violations (TEST-115)
<2> Cell constant during scan violations (TEST-142)
<3> Cell is uncontrollable during scan violations (TEST-302)
<4> Cell does not capture violations (TEST-310)
The first violation is because of the tri-state output port of RAM,
and the rest three violations are of the nonscan cells, so I ignore
there violations.

2. ATPG using TetraMax for pre-layout netlist
There were not any error during the atpg process, except N20/N23 .

3. Simulated the test patterns with VCS
Simulated all the test patterns with No Errors.

4. P&R with Astro , reordering the scan chains , and output the post-layout netlist

5. I run Formality with the post-layout netlist and the original netlist .
Because scan chains were reordered , I can't use the pre-layout netlist as the golden netlist. And the post-layout netlist is all right.

6. I run PrimeTime with the post-layout netlist.
There were only several clock gated hold time violations. Because I use a funcitonal input as a test clock input . And there were no setup/hold time violations!

7. I run TetraMax with the post-layout netlist as before, and it generated the
test patterns successfully.

8. I used the testbench (parallel) generated by TetraMax to run the simulations with VCS, and it failed!
I didn't use the SDF file! I run simulation with zero timing delay!

 

[rameshsuthapalli]

scan simulation failure no timing violation

Hi leeguoxian,

u r flow is correct upto 7 .
8 step is wrong step.bcz we must use the MAX or min delay mode with the SDF annotations. since the simulator will assume in such a way that each cell will contribute an unit delay and it will analize the path so that there may be a chance of getting the setup and hold problems in the postlay so i recomende to use atpg simulations in the postlayout must be done in both min and max delay mode of the simulator with the proper sdf file.
regards
rameshs

 

[leeguoxian]

spf simulation ncverilog

Hi leeguoxian,

u r flow is correct upto 7 .
8 step is wrong step.bcz we must use the MAX or min delay mode with the SDF annotations. since the simulator will assume in such a way that each cell will contribute an unit delay and it will analize the path so that there may be a chance of getting the setup and hold problems in the postlay so i recomende to use atpg simulations in the postlayout must be done in both min and max delay mode of the simulator with the proper sdf file.
regards
rameshs

Dear Rameshs
Yes , I agreed with u that we must simulate with the SDF file for post-layout netlist.
But how could it pass if simulations without SDF file failed?
I think the only difference of ATPG between prelay and postlay is the netlist,
if simulation of prelay netlist was good, using the same script, simulation of postlay netlist should be good too , right ?

regards
leeguoxian

 

[jackson_peng]

tetramax rule n2

after checking your flow, i give my suggestion as follows:

1. have you ever bypass the RAM module in scan mode? the high impedence output would jeoperdize the downstream scan-reg. alternatively, you can exclude the RAM drived registers from scan insertion.
also reg with other violation should be exculde as well.

2. do "check_test" on the post-netlist of Astro, to see whether the report errors are the same as pre-netlist. it just guarantees that the PR step didn't change the scanability of your design.

3. as i told before. you can do one more round PR with your scan-chain order perserved. and do formality on the post-netlist and pre-netlist. it can guarantee that the general PR steps won't affact the scanability, which also implies that the problem might from your reorder steps.

by the way. i am not sure whether Astro can detect the scan-chain correctly with netlist still contain dft errors.

regards.

 

[rameshsuthapalli]

atpg pattern parallel

Hi leeguoxian,

i will explain u. in the post layout the if u run in the no delay mode.these r the problems compared to the prelayout simulations.
1)take this case there is a path directly going from q pin to next flop d pin with a simple and gate. in the prelayout stage there is no buffers(clock tree) in the clock path. so there is no hold violation.
2) in the abouve case take it in postlay stage the tool inserted two more buffs in the clock path compared compared to prelayout .
it will think that the capture flop is under hold problem. so the atpg simulations will failed.
regards
rameshs

 

[leeguoxian]

spf file in atpg

Hi leeguoxian,

i will explain u. in the post layout the if u run in the no delay mode.these r the problems compared to the prelayout simulations.
1)take this case there is a path directly going from q pin to next flop d pin with a simple and gate. in the prelayout stage there is no buffers(clock tree) in the clock path. so there is no hold violation.
2) in the abouve case take it in postlay stage the tool inserted two more buffs in the clock path compared compared to prelayout .
it will think that the capture flop is under hold problem. so the atpg simulations will failed.
regards
rameshs

Dear Rameshs:
I agree with u that if there are hold/setup time violation, atpg simualtions will failed. but I didn't use the SDF file in simulations.
Does VCS consider setup/hold time violations even if I didn't use the SDF file?
Actually, I did run simulation with SDF file, but it fail again. And I run PrimeTime to check its timing, no setup/hold violations.
I think : for post layout , we first run simulation without SDF file. If there isn't any error , we can continue to simulatie with SDF file. If simulation fails without using SDF file, I think there must be something wrong with the TetraMax process.

 

[rameshsuthapalli]

sdf atpg simulations

Hi leeguoxian,

the vcs simulator will consider the unit delta delay for all the cells for caluculationg the simulation results.
u can see that while running the simulator it is saying that 0.5 or 1 is conistantly assigned as delay for each cell. the no delaymode will not give any problem for setup but it will give problem for hold in postlay simulations.

plz run the STA with out the false paths and multy cycle paths.
so u will get the violation as some x with the clock time period ad Y.
then run the simulations with the period of the scan clock as "X+Y".
that means u must re genetarate the tpg vectors with scan clock havins X+Y period.
if problem is still there then see wether there is any hold violations in the above sta reports.
regards
rameshs

 

[leeguoxian]

all_bidirectionals

Hi leeguoxian,

the vcs simulator will consider the unit delta delay for all the cells for caluculationg the simulation results.
u can see that while running the simulator it is saying that 0.5 or 1 is conistantly assigned as delay for each cell. the no delaymode will not give any problem for setup but it will give problem for hold in postlay simulations.

plz run the STA with out the false paths and multy cycle paths.
so u will get the violation as some x with the clock time period ad Y.
then run the simulations with the period of the scan clock as "X+Y".
that means u must re genetarate the tpg vectors with scan clock havins X+Y period.
if problem is still there then see wether there is any hold violations in the above sta reports.
regards
rameshs

Dear Rameshs :
Thanks for your advice, I will have a try.
But I don't understand, if timing delay is zero in my verilog library, is VCS still timging sensetive ? And it seems there is not any setup/hold time violation in post-layout netlist .
In the TetraMax process, I didn't use any file including timing information, so I think TetraMax generate the test pattern without consider the timing. As a result ,
simulaion should be pass without timing , right ?
And I tried another design, simulation failed using the netlist generated by DFT .
I think there must be somthing wrong with my TetraMax script.

Here is my script :

read netlist -delete
read netlist $Path/design.v

read netlist $Path/STD.v -lib
read netlist $Path/IO.v -lib
read netlist $Path/IP.v -lib
# I didn't read in the RAM/ROM verilog lib.

set build -empty_box ROM
set build -empty_box u_rom (u_rom is instance of ROM)
set build -empty_box RAM
set build -empty_box u_ram
set build -black_box IP
set build -black_box u_IP

run build_model TOP

set drc $Path/design.spf

run drc $Path/design.spf

report rules -fail

add faults -all

set pat internal

set atpg -abort 5 -merge off

run atpg -auto

set faults -fault_coverage
report summaries faults

write patterns design_dpv.v -internal -format verilog -parallel -replace

exit
==================================================
Following are the rules failed:
N2, N20, N23
B6, B7, B8 ,B9, B10, B12,B18,B23
S19
C2,C16,C17,C19,C22,C25
V12,V16,V18
X1
===================================================

regards
leeguoxian

 

[rameshsuthapalli]

Hi leeguoxian,
i think u r script is fine but when ever u porovide the spf file. the tetra max will see the spf file and it take the inforamtion(clock period and its waveform,input triggering time,output capture time) from the spf file. so plz modifie the spf file according to the new clock frequency as i suggested previously and make triggering time at 0 and 95%of the clock period for the input triggertime and for output capture time respectively.

Timing {
WaveformTable "_default_WFT_" {
Period '100ns';
Waveforms {
"all_inputs" { 0 { '0ns' D; } }
"all_inputs" { 1 { '0ns' U; } }
"all_inputs" { Z { '0ns' Z; } }
"all_inputs" { N { '0ns' N; } }
"all_bidirectionals" { 0 { '0ns' D; } }
"all_bidirectionals" { 1 { '0ns' U; } }
"all_bidirectionals" { N { '0ns' N; } }
"all_bidirectionals" { Z { '0ns' Z; } }
"all_bidirectionals" { T { '0ns' Z; '95ns' T; } }
"all_bidirectionals" { X { '0ns' Z; '95ns' X; } }
"all_bidirectionals" { H { '0ns' Z; '95ns' H; } }
"all_bidirectionals" { L { '0ns' Z; '95ns' L; } }
"all_outputs" { X { '0ns' X; } }
"all_outputs" { H { '0ns' X; '95ns' H; } }
"all_outputs" { T { '0ns' X; '95ns' T; } }
"all_outputs" { L { '0ns' X; '95ns' L; } }
"DBHV0" { P { '0ns' D; '45ns' U; '55ns' D; } }
}
}
}

in the above is the peace spf file in which my clok period id 100ns so my triggering point is at 95ns for output and 0ns for the input somodifie ur spf accordingly.

i think u r problem will be solved by this

regards
rameshs