ATA/ATAPI low level question

I am trying to figure out what exactly is happening
on ATA/ATAPI bus right after power-on. From what
I understand - host shoud send RESET command, then
after some predetermined time send query to identify
devices on the bus. But in reality, it does not look
much like that. I have connected logic analyzer, and
from what I see there are flying some READ commands
before any WRITE (to send a command) happen. Why ?

Anyone know/understand what should be the actual
sequence of events ?

The start-up sequence is discussed in a paragraph Power-on and hardware reset protocol of the ATA specification.

Correct, true in every version that I have here. The problem is that
they state:

"If the host asserts RESET-, regardless of the power management mode,
the device shall execute the hardware reset protocol. (...) A host should
issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command
after the power-on or hardware reset protocol has completed to determine
the current status of features implemented by the device(s)."

Now, what I see on LA is that after RESET, there is few READ commands
sent from HOST, before it issue 0xA0 (packet command (why?)), and then
finally 0xA1 (IDENTIFY PACKET DEVICE).

So...
- why there are READs ? after RESET, but before IDENT ?
- where I can find _that_ explained ?
- what am I missing ?