asynchronous timing arc characrterization

Thread starter nitin kala
Start date Feb 16, 2013

Status: Not open for further replies.

Feb 16, 2013

nitin kala

Junior Member level 1

Hi all,

While doing removal & recovery time characterization for 45nm library, i find erroneous results for high clock pin & CDN/SDN pin transition time.
Please suggest me what measures can be taken for characterizing flops with higher transition times values of clock signal
or asynchronous signals ( reset/clear ).

Regards,
Nitin

Status: Not open for further replies.

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asynchronous timing arc characrterization

nitin kala

Junior Member level 1

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