Asynchronous Logic ? (circuit added)

[ulaska]

i will use XC9572XL.
i draw the PLD circuit in Xilinx WebPack ISE 7.1 Project Navigator.

it doesnt gives any error. But some warnings about some lines in asynchronous .


"Possible asynchronous logic: Clock pin 'FIO3.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'."


what can i do?

Thanks.

 

[nand_gates]

Re: Asynchronous Logic ?

Can you post ur circuit here???

 

[nittinsharma80]

Re: Asynchronous Logic ?

yes the circuit can help in pin pointing the problem

 

[soccer]

Asynchronous Logic ?

it is a error , you have assigned multiple signals on one wire.

 

[ulaska]

Re: Asynchronous Logic ?

i attached the circuit.

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'FIO3.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'FIO2.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'FIO1.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'FIO0.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'XLXI_2/XLXN_20.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'XLXI_2/XLXN_21.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'XLXI_2/XLXN_22.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'XLXI_2/XLXN_23.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.
Possible asynchronous logic: Clock pin 'PRES.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'.

Performance Summary
Min. Clock Period 13.000 ns.
Max. Clock Frequency (fSYSTEM) 76.923 MHz.
Limited by Clock Pulse Width for CS2_INV
Pad to Pad Delay (tPD) 15.700 ns.
Setup to Clock at the Pad (tSU) 1.600 ns.
Clock Pad to Output Pad Delay (tCO) 15.900 ns.

 

[echo47]

It is warning you that your design has a gated clock (at your octal D-flop).
A gated clock can work if you are careful, but it is not good design practice.

It would be better to choose a D-flop that has a clock enable input, and use it instead of gating your clock. However, I don't see an obvious clock signal anywhere in your schematic.

 

[ulaska]

thanks,
this design is not of mine, this is working on Altera EPM7064.

there is a hyperstone 120 MHz processor , davicom 100mbit ethernet controller, uart, flash, sdram on the main board, and this PLD is external devices' chip selector etc.

are you sure, this problem is beacuse of the "gated clock" ?

thank you.