Asynchronous fifo solve the error

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Code Verilog - [expand]
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module fifo_top
    #(
    parameter DEPTH = 32,
    WIDTH = 32,
    ADDR = 5
    )
    (
    input wire write, wreset_b, wclk, read, rreset_b, rclk,
    input wire [WIDTH-1:0] wdata,
    output wire [WIDTH-1:0] rdata,
    output wire rempty, wfull
    );
    
    // function to convert from gray to binary
    function [ADDR:0] G2B_Fn;
    input [ADDR:0] gray;
 reg [ADDR:0] binary;
    integer i;
    begin
    binary[ADDR] = gray [ADDR]; 
    for (i=ADDR-1;i >= 0;i=i-1)
   binary[i+1] = (binary[i] ^ gray[i+1]);
    
    G2B_Fn = binary;
    end 
    endfunction
    
    // declare connecting wires
    wire [ADDR:0]   wptr_b,wptr_g,  // binary and gray signals from write pointer
                    rptr_b,rptr_g;  // binary and gray signals from read pointer
    
    reg [ADDR:0]   g2b_wd_op,           // function G2B_Fn output in the write domain
                    g2b_rd_op;          // function G2B_Fn output in the read domain
    wire [ADDR:0]   g2b_wd_ip,          // function G2B_Fn input in the write domain
                    g2b_rd_ip;          // function G2B_Fn input in the read domain
    
    //assign intermediate wires
    always @(g2b_wd_ip or g2b_rd_ip)
        begin
            g2b_wd_op = G2B_Fn(g2b_wd_ip);  
        g2b_rd_op = G2B_Fn(g2b_rd_ip);
        end
    // instantiate write pointer
    pointer wptr(
    .clk(wclk),
    .reset_b(wreset_b),
    .op(write),
    .fifo_status(wfull),
    .gray(wptr_g),
    .binary(wptr_b)
    );
    
    //instantiate read pointer
    pointer rptr(
    .clk(rclk),
    .reset_b(rreset_b),
    .op(read),
    .fifo_status(rempty),
    .gray(rptr_g),
    .binary(rptr_b)
    );
                    
    //instantiate memory module
        memory m1(
        .clk(wclk),
        .reset_b(wreset_b),
        .write(write),
        .wfull(wfull),
        .waddr(wptr_b[ADDR-1:0]),
        .raddr(rptr_b[ADDR-1:0]),
        .wdata(wdata),
        .rdata(rdata)
        ); 
    
    
    //instantiate read->write synchronizer
    sync_r2w syncr2w(
    .clk(wclk),
    .reset_b(wreset_b),
    .rptr(rptr_g),
    .rptr_wr(g2b_wd_ip)
    );
    
    //instantiate write->read synchronizer
    sync_w2r syncw2r(
    .clk(rclk),
    .reset_b(rreset_b),
    .wptr(wptr_g),
    .wptr_rd(g2b_rd_ip)
    );
    
        
    //instantiate write domain comparator
    compare_wr cmp_wr(
    .rptr(g2b_wd_op),
    .wptr(wptr_b),
    .full(wfull)
    );
    
    //instantiate read domain comparator
    compare_rd cmp_rd(
    .rptr(rptr_b),
    .wptr(g2b_rd_op),
    .empty(rempty)
    );              
    
    
endmodule
 
module pointer
    #(
    parameter ADDR = 5  // parameterized size of pointers
    )
    (
    input wire clk,reset_b,op,fifo_status, // input-output declaration
      output reg [ADDR:0] gray,binary
     
    ); 
    integer i;
    
    always@(posedge clk, negedge reset_b)
        begin
        if(~reset_b)
            begin
            binary = 'd0;
            gray = 'd0;
            end 
        else if(op & ~fifo_status)
            binary <= binary + 1; 
        end
    
    always @(binary)
        begin
            gray[ADDR] = binary[ADDR];
            for (i=ADDR-1;i>=0;i=i-1)
    gray[i] = binary[i] ^ binary[i+1];
        end
        
endmodule   
 
module compare_wr
    #(
     parameter ADDR = 5 // declare parameter for memory address
    )                 
    (
    input wire [ADDR:0] rptr,wptr,  // declare inputs and outputs
    output wire full
    );  
    //check for full condition: Write pointer has wrapped around but read pointer has not
    
        assign full = (wptr[ADDR] != rptr[ADDR]) & (wptr[ADDR-1:0] == rptr[ADDR-1:0]);
endmodule 
 
module memory
    #(
    parameter DEPTH = 32, // parameter declaration
    WIDTH = 32,
    ADDR = 5
    )
    (
    input wire clk, reset_b, write, wfull, // input - output declaration
    input wire [ADDR-1:0] waddr, raddr,
    input wire [WIDTH-1:0] wdata,
    output wire [WIDTH-1:0] rdata
    );
    
    integer i;
    // creating memory
    reg [WIDTH-1:0] sram [DEPTH-1:0];
    
    // writing in the memory
    always @(posedge clk, negedge reset_b)
        begin
        if(~reset_b)
            begin
            for(i=0;i<DEPTH;i = i+1)
                sram[i] <= 'h0;
            end
        else if(write & ~wfull)
            sram[waddr] <= wdata;
        end 
    
    // reading a memory location
    assign rdata = sram[raddr];
endmodule
 
// to synchronize from fast clock domain to slow clock domain (write -> read)
module sync_w2r 
    #( 
    parameter ADDR = 5
    )
    (
    input wire clk, reset_b,
    input wire [ADDR:0] wptr,
    output reg [ADDR:0] wptr_rd
    );
    
    reg [ADDR:0] q;
    always @(posedge clk or negedge reset_b)
        begin
            if(~reset_b)
                begin
                    q <= 'd0;
                    wptr_rd <= 'd0;
                end
            else
                begin
                    q <= wptr;
                    wptr_rd <= q;
                end
        end
    
endmodule
 
// to synchronize from slow clock domain to fast clock domain (read -> write)
module sync_r2w
    #(
    parameter ADDR = 5
    )
    (
    input wire clk, reset_b,
    input wire [ADDR:0] rptr,
    output reg [ADDR:0] rptr_wr
    ); 
    
    reg [ADDR:0] q;
    always @(posedge clk or negedge reset_b)
        begin
            if(~reset_b)
                begin
                    q <= 'd0;
                    rptr_wr <= 'd0;
                end
            else
                begin
                    q <= rptr;
                    rptr_wr <= q;
                end
        end
endmodule
    
    
module compare_wr
    #(
     parameter ADDR = 5 // declare parameter for memory address
    )                 
    (
    input wire [ADDR:0] rptr,wptr,  // declare inputs and outputs
    output wire full
    );  
    //check for full condition: Write pointer has wrapped around but read pointer has not
    
        assign full = (wptr[ADDR] != rptr[ADDR]) & (wptr[ADDR-1:0] == rptr[ADDR-1:0]);
endmodule 
 
module compare_rd
    #(
     parameter ADDR = 5 // declare parameter for memory address
    )                 
    (
    input wire [ADDR:0] rptr,wptr,  // declare inputs and outputs
    output wire empty
    );  
    //check for full condition: WRITE and READ pointers have NOT wrapped around
        
        assign  empty = wptr[ADDR:0] == rptr[ADDR:0];
endmodule
 
//TEST BENCH IS
`include "fifo_top.v"
`include "pointer.v"
`include "memory.v"    
`include "sync.v"
 `include "comparator.v"
module fifo_top_tb
 
reg write,wreset_b,wclk,read,rreset_b,rclk;
reg[31:0] wdata;
wire[31:0]rdata;
wire rempty,wfull;
  fifo_top ff(.write(write),.wreset_b(wreset_b),.wclk(wclk),.read(read),.rreset_b(rreset_b),.rclk(rclk),.wdata(wdata),.rdata(rdata),.rempty(rempty),.wfull(wfull));
 
  
  
  initial
    begin
      #5 @(posedge wclk or negedge wreset_b or negedge rreset_b)
   begin   write=1;
      wdata=0000001;
      #2wdata=00000010;
      #2wdata=00000011;
#1$display("rdata=%b,rempty=%b,wfull=%b",rdata,rempty,wfull);
     
      #2 read=1;
       #2wdata=00000100;
      #2wdata=00000101;
     #2 read=1;
  
        #1$display("rdata=%b,rempty=%b,wfull=%b",rdata,rempty,wfull);
      end 
      end  
        
      endmodule


ERRORS IS

Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 8: token is 'reg'
reg write,wreset_b,wclk,read,rreset_b,rclk;
^
Click to expand...
 
Last edited by a moderator:

Review sv/verilog syntax rules, semicolon missing.
Code: 
module fifo_top_tb[COLOR="#FF0000"];[/COLOR]
 

yes, i have given it but after that when i am executing it is not displaying the output
 

if you see here the code is executed but it is not displaying the ouptut.
 

Why do you expect the testbench to do anything?

Your testcase doesn't do anything, it just sits there with X's on every signal applied to the UUT.

Learn to write a working testbench with clocks and BFMs.

e.g. generating a testbench clock.
Code Verilog - [expand]
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initial begin
  clk = 0;
  forever #5 clk = ~clk; // for a clock with a 10 time unit period
end
 

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