asynchronous FIFO help

Hi,
i am designing asynchronous FIFO with the following specs:
write clock = 166 Mhz
read clock = 66 Mhz

assuming reading and writing occur consequently each clock cycle for reading and writing

i am asking how to calculate FIFO depth ? i think i need at least 100 locations, is it right ?

one more question : what corner cases should i verify for proper functionality of the FIFO?

thanks in advance

Hi,

https://www.edaboard.com/threads/323344/

Klaus

hi KlausST ,

what is meant by " data burst size "

thank you in advance

- - - Updated - - -

i have one more question

does number of idle cycles between data burst matter ?

so if i have:
a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order).

will have the same depth of:
a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 81 clocks. In other words, a 81 input clock will carry only 80 data and the other clock cycle does not carry data (data is scattered in any order).
?

Data burst size is the amount of continuous data you are injecting into the fifo.If you are writing every 10 cycles to fifo in which only the first 5 cycles contain valid data, then your burst size is 5.Idle cycles in a burst do matter.

For your original question, first find out the data rates on the input as well as the output sides. Only if the output rate is higher than the input will it be feasible to use a fifo in the first place.

Once you have found out that a fifo can be used, do an analysis for the fastest write scenario and the slowest read scenario. This will help you find the depth.

what is the difference between data rate at input and output side and the data burst size ? could you please explain using a numerical example ?

could you please answer the updated part of the last post
"
i have one more question

does number of idle cycles between data burst matter ?

so if i have:
a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order).

will have the same depth of:
a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 81 clocks. In other words, a 81 input clock will carry only 80 data and the other clock cycle does not carry data (data is scattered in any order).
?
"

abdalrahman_ehsan said:

what is meant by " data burst size "

Click to expand...

New data is sent on each clock in a contiguous uninterrupted block. These bursts are interspersed with gaps of no new data on each clock.

does number of idle cycles between data burst matter ?

Click to expand...

Yes, this will effectively change the rate at which data is written to the FIFO. e.g. 100 MHz input clock with data+idle, results in an effective write rate of 50 MHz, so if the reads are done continuously at 80 MHz you will underflow the FIFO eventually.

so if i have:
a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order).

Click to expand...

This case does not matter. You would never design to some arbitrary random write/read scheme. You design for worst case if you want the FIFO to be big enough to never overflow.

will have the same depth of:
a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 81 clocks. In other words, a 81 input clock will carry only 80 data and the other clock cycle does not carry data (data is scattered in any order).
?

Click to expand...

Now this is almost worst case.
Using your 100 MHz write clock with 80 MHz read.
Given the following situation:
1. Reads are continuous on every clock cycle at 80 MHz
2. Writes are done in bursts with an aggregate rate equal to writing at 80 MHz continuously.

If we allow the burst transfers in the 100 clocks to have arbitrary alignment then the worst case alignment would be 160 writes at 100 MHz (over an interval of 200 100 MHz clock cycles). So the ordering of the idles and data for 200 100 MHz clock cycles would look like: 20i-80d-80d-20i (where i=idles, d=data).

This means that we could potentially write for 160 100 MHz clock cycles...i.e. write continuously for 1.6 us. During this time we read data at 80 MHz so we can read 128 (1.6 us /12.5 ns) words of data from the FIFO during those 160 100 MHz clock cycles. As we wrote 160 but only read 128 the FIFO has to be larger than 32 (160-128) deep. In actuality you will need at least a depth of 35+ to accommodate the clock domain crossings in the FIFO for the pointers, therefore in this case you would probably implement a 64 deep FIFO.

Hopefully you could follow along with this explanation.

Regards

- - - Updated - - -

If you have guaranteed idle cycles between bursts then the calculation will change somewhat as for every 5 100 MHz clock cycles of idle time you add will reduce the depth of the FIFO by 4 words.

thank you for your helpful answer

for further understanding i wish to ask some more questions

- what is the condition on write and read rates to avoid overflow and underflow ?
- should read rate be higher than write rate to use FIFO ?

- i don't understand the last update
"
If you have guaranteed idle cycles between bursts then the calculation will change somewhat as for every 5 100 MHz clock cycles of idle time you add will reduce the depth of the FIFO by 4 words
"

- if my fifo and connected system has full and empty control signals i shouldn't worry about fifo depth, is that right ?

thank you in advance

abdalrahman_ehsan said:

- what is the condition on write and read rates to avoid overflow and underflow ?
- should read rate be higher than write rate to use FIFO ?

Click to expand...

Write rate == Read rate, along with even distribution of the write and reads (no bursts), then start reading after writing half of the FIFO depth. IF the rates are equal and reads and writes are uniformly distributed without interruption then the FIFO will never over/under flow.

otherwise...You should use the flags.

- if my fifo and connected system has full and empty control signals i shouldn't worry about fifo depth, is that right ?

Click to expand...

This will result in stalling the datapath. For the full case it stalls the input datapath to the FIFO and in the empty case it stalls the output datapath. If your design can tolerate datapath stalls then this would allow you use a much smaller FIFO.

- i don't understand the last update
"
If you have guaranteed idle cycles between bursts then the calculation will change somewhat as for every 5 100 MHz clock cycles of idle time you add will reduce the depth of the FIFO by 4 words"

Click to expand...

5 100 MHz clocks is 50 ns, in the same 50 ns you can have 4 80 MHz clocks. So if you stop writing for 5 100 MHz clocks you will have read 4 words from the FIFO at 80 MHz.

Regards

ads-ee said:

Given the following situation:
1. Reads are continuous on every clock cycle at 80 MHz
2. Writes are done in bursts with an aggregate rate equal to writing at 80 MHz continuously.

If we allow the burst transfers in the 100 clocks to have arbitrary alignment then the worst case alignment would be 160 writes at 100 MHz (over an interval of 200 100 MHz clock cycles). So the ordering of the idles and data for 200 100 MHz clock cycles would look like: 20i-80d-80d-20i (where i=idles, d=data).

This means that we could potentially write for 160 100 MHz clock cycles...i.e. write continuously for 1.6 us. During this time we read data at 80 MHz so we can read 128 (1.6 us /12.5 ns) words of data from the FIFO during those 160 100 MHz clock cycles. As we wrote 160 but only read 128 the FIFO has to be larger than 32 (160-128) deep. In actuality you will need at least a depth of 35+ to accommodate the clock domain crossings in the FIFO for the pointers, therefore in this case you would probably implement a 64 deep FIFO.

Hopefully you could follow along with this explanation.

Regards

- - - Updated - - -

If you have guaranteed idle cycles between bursts then the calculation will change somewhat as for every 5 100 MHz clock cycles of idle time you add will reduce the depth of the FIFO by 4 words.

Click to expand...

Excellent analysis.. Thanks :0