asynchronous FIFO design

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//'EqualAddresses' logic:
      assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
  
      //'Quadrant selectors' logic:
    assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &                           (pNextWordToWrite[ADDRESS_WIDTH-1] ^  pNextWordToRead[ADDRESS_WIDTH-2]);
                              
      assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^  pNextWordToRead[ADDRESS_WIDTH-1]) &                          (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
                           
       //'Status' latch logic:
      always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
          if (Rst_Status | Clear_in)
              Status = 0;  //Going 'Empty'.
          else if (Set_Status)
              Status = 1;  //Going 'Full'.
              
      //'Full_out' logic for the writing port:
      assign PresetFull = Status & EqualAddresses;  //'Full' Fifo.
      
      always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
          if (PresetFull)
             Full_out <= 1;
           else
             Full_out <= 0;
            
     //'Empty_out' logic for the reading port:
    assign PresetEmpty = ~Status & EqualAddresses;  //'Empty' Fifo.
    
      always @ (posedge RClk, posedge PresetEmpty)  //D Flip-Flop w/ Asynchronous Preset.
          if (PresetEmpty)
            Empty_out <= 1;
          else
            Empty_out <= 0;